Module Name: src
Committed By: riz
Date: Tue Jan 26 01:25:33 UTC 2016
Modified Files:
src/sys/arch/sparc64/dev [netbsd-7]: schizo.c schizoreg.h schizovar.h
Log Message:
Pull up following revision(s) (requested by jdc in ticket #1064):
sys/arch/sparc64/dev/schizo.c: revision 1.34
sys/arch/sparc64/dev/schizo.c: revision 1.35
sys/arch/sparc64/dev/schizovar.h: revision 1.7
sys/arch/sparc64/dev/schizoreg.h: revision 1.10
sys/arch/sparc64/dev/schizoreg.h: revision 1.11
add some tomatillo specific information to schizo_pbm_regs.
Set the target JPID for all interrupts on Tomatillo.
If the "ino-bitmap" property is available, use it to route error interrupts.
Minor cosmetic changes.
Add register printing when DEBUG is defined.
Use __BIT() for some masks to fix the sparc build.
No binary changes.
To generate a diff of this commit:
cvs rdiff -u -r1.31.8.1 -r1.31.8.2 src/sys/arch/sparc64/dev/schizo.c
cvs rdiff -u -r1.9 -r1.9.14.1 src/sys/arch/sparc64/dev/schizoreg.h
cvs rdiff -u -r1.6 -r1.6.14.1 src/sys/arch/sparc64/dev/schizovar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/dev/schizo.c
diff -u src/sys/arch/sparc64/dev/schizo.c:1.31.8.1 src/sys/arch/sparc64/dev/schizo.c:1.31.8.2
--- src/sys/arch/sparc64/dev/schizo.c:1.31.8.1 Mon Nov 10 17:59:57 2014
+++ src/sys/arch/sparc64/dev/schizo.c Tue Jan 26 01:25:32 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: schizo.c,v 1.31.8.1 2014/11/10 17:59:57 snj Exp $ */
+/* $NetBSD: schizo.c,v 1.31.8.2 2016/01/26 01:25:32 riz Exp $ */
/* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */
/*
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: schizo.c,v 1.31.8.1 2014/11/10 17:59:57 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: schizo.c,v 1.31.8.2 2016/01/26 01:25:32 riz Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -74,6 +74,10 @@ static int schizo_match(device_t, cfdata
static void schizo_attach(device_t, device_t, void *);
static int schizo_print(void *aux, const char *p);
+#ifdef DEBUG
+void schizo_print_regs(int unit, int what);
+#endif
+
CFATTACH_DECL_NEW(schizo, sizeof(struct schizo_softc),
schizo_match, schizo_attach, NULL, NULL);
@@ -143,8 +147,8 @@ schizo_attach(device_t parent, device_t
struct schizo_pbm *pbm;
struct iommu_state *is;
struct pcibus_attach_args pba;
- uint64_t reg, eccctrl;
- int *busranges = NULL, nranges;
+ uint64_t reg, eccctrl, ino_bitmap;
+ int *busranges = NULL, nranges, *ino_bitmaps = NULL, nbitmaps;
char *str;
bool no_sc;
@@ -180,6 +184,9 @@ schizo_attach(device_t parent, device_t
if (pbm == NULL)
panic("schizo: can't alloc schizo pbm");
+#ifdef DEBUG
+ sc->sc_pbm = pbm;
+#endif
pbm->sp_sc = sc;
pbm->sp_regt = sc->sc_bustag;
@@ -194,11 +201,25 @@ schizo_attach(device_t parent, device_t
if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr,
ma->ma_reg[0].ur_len,
BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) {
- aprint_error(": failed to interrupt map registers\n");
+ aprint_error(": failed to map interrupt registers\n");
kmem_free(pbm, sizeof(*pbm));
return;
}
+#ifdef DEBUG
+ /*
+ * Map ichip registers
+ */
+ if (sc->sc_tomatillo)
+ if (bus_space_map(sc->sc_bustag, ma->ma_reg[3].ur_paddr,
+ ma->ma_reg[3].ur_len,
+ BUS_SPACE_MAP_LINEAR, &pbm->sp_ichiph)) {
+ aprint_error(": failed to map ichip registers\n");
+ kmem_free(pbm, sizeof(*pbm));
+ return;
+ }
+#endif
+
if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range),
&pbm->sp_nrange, (void **)&pbm->sp_range))
panic("schizo: can't get ranges");
@@ -207,7 +228,7 @@ schizo_attach(device_t parent, device_t
(void **)&busranges))
panic("schizo: can't get bus-range");
- aprint_normal(": \"%s\", version %d, ign %x, bus %c %d to %d\n",
+ aprint_normal(": %s, version %d, ign %x, bus %c %d to %d\n",
sc->sc_tomatillo ? "Tomatillo" : "Schizo", sc->sc_ver,
sc->sc_ign, pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]);
aprint_naive("\n");
@@ -304,20 +325,34 @@ schizo_attach(device_t parent, device_t
SCZ_PCIDIAG_D_INTSYNC);
schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg);
- if (pbm->sp_bus_a)
+ if (prom_getprop(sc->sc_node, "ino-bitmap", sizeof(int), &nbitmaps,
+ (void **)&ino_bitmaps)) {
+ /* No property - set defaults (double map UE, CE, SERR). */
+ if (pbm->sp_bus_a)
+ ino_bitmap = __BIT(SCZ_PCIERR_A_INO);
+ else
+ ino_bitmap = __BIT(SCZ_PCIERR_B_INO);
+ ino_bitmap |= __BIT(SCZ_UE_INO) | __BIT(SCZ_CE_INO) |
+ __BIT(SCZ_SERR_INO);
+ } else
+ ino_bitmap = (uint64_t) ino_bitmaps[1] << 32 | ino_bitmaps[0];
+ DPRINTF(SDB_INTR, ("ino_bitmap=0x%016" PRIx64 "\n", ino_bitmap));
+
+ if (ino_bitmap & __BIT(SCZ_PCIERR_A_INO))
schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error,
pbm, SCZ_PCIERR_A_INO, "pci_a");
- else
+ if (ino_bitmap & __BIT(SCZ_PCIERR_B_INO))
schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error,
pbm, SCZ_PCIERR_B_INO, "pci_b");
-
- /* double mapped */
- schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO,
- "ue");
- schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO,
- "ce");
- schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc,
- SCZ_SERR_INO, "safari");
+ if (ino_bitmap & __BIT(SCZ_UE_INO))
+ schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO,
+ "ue");
+ if (ino_bitmap & __BIT(SCZ_CE_INO))
+ schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO,
+ "ce");
+ if (ino_bitmap & __BIT(SCZ_SERR_INO))
+ schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc,
+ SCZ_SERR_INO, "safari");
if (sc->sc_tomatillo) {
/*
@@ -567,6 +602,7 @@ schizo_set_intr(struct schizo_softc *sc,
schizo_pbm_write(pbm, mapoff,
ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT));
+ schizo_pbm_write(pbm, clroff, 0);
}
bus_space_tag_t
@@ -755,8 +791,9 @@ schizo_pci_intr_map(const struct pci_att
struct schizo_pbm *pbm = pa->pa_pc->cookie;
struct schizo_softc *sc = pbm->sp_sc;
+ DPRINTF(SDB_INTMAP, ("IGN %x", *ihp));
*ihp |= sc->sc_ign;
- DPRINTF(SDB_INTMAP, ("returning IGN adjusted to %x\n", *ihp));
+ DPRINTF(SDB_INTMAP, (" adjusted to %x\n", *ihp));
return (0);
}
@@ -779,7 +816,7 @@ schizo_intr_establish(bus_space_tag_t t,
if (ih == NULL)
return (NULL);
- DPRINTF(SDB_INTR, ("\n%s: ihandle %d level %d fn %p arg %p\n", __func__,
+ DPRINTF(SDB_INTR, ("\n%s: ihandle %x level %d fn %p arg %p\n", __func__,
ihandle, level, handler, arg));
if (level == IPL_NONE)
@@ -834,6 +871,7 @@ schizo_intr_establish(bus_space_tag_t t,
DPRINTF(SDB_INTR, ("; read intrmap = %016qx",
(unsigned long long)imap));
imap |= INTMAP_V;
+ imap |= (CPU_UPAID << INTMAP_TID_SHIFT);
DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr));
DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n",
(unsigned long long)imap));
@@ -864,3 +902,173 @@ schizo_pci_intr_establish(pci_chipset_ta
DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie));
return (cookie);
}
+
+#ifdef DEBUG
+void
+schizo_print_regs(int unit, int what)
+{
+ device_t dev;
+ struct schizo_softc *sc;
+ struct schizo_pbm *pbm;
+ const struct schizo_regname *r;
+ int i;
+ u_int64_t reg;
+
+ dev = device_find_by_driver_unit("schizo", unit);
+ if (dev == NULL) {
+ printf("Can't find device schizo%d\n", unit);
+ return;
+ }
+
+ if (!what) {
+ printf("0x01: Safari registers\n");
+ printf("0x02: PCI registers\n");
+ printf("0x04: Scratch pad registers (Tomatillo only)\n");
+ printf("0x08: IOMMU registers\n");
+ printf("0x10: Streaming cache registers (Schizo only)\n");
+ printf("0x20: Interrupt registers\n");
+ printf("0x40: I-chip registers (Tomatillo only)\n");
+ return;
+ }
+ sc = device_private(dev);
+ pbm = sc->sc_pbm;
+ printf("%s (leaf %c) registers:\n", device_xname(sc->sc_dev),
+ pbm->sp_bus_a ? 'A' : 'B');
+
+ printf(" Safari registers:\n");
+ if (what & 0x01) {
+ for (r = schizo_regnames; r->size != 0; ++r)
+ for (i = 0; i <= r->n_reg; i += r->size) {
+ if ((!sc->sc_tomatillo &&
+ !(r->type & REG_TYPE_SCHIZO)) ||
+ (sc->sc_tomatillo &&
+ !(r->type & REG_TYPE_TOMATILLO)))
+ continue;
+ switch (r->size) {
+ case 1:
+ reg = schizo_read_1(sc, r->offset + i);
+ break;
+ case 8:
+ /* fallthrough */
+ default:
+ reg = schizo_read(sc, r->offset + i);
+ break;
+ }
+ printf("0x%06" PRIx64 " = 0x%016" PRIx64 " (%s",
+ r->offset + i, reg, r->name);
+ if (r->n_reg)
+ printf(" %d)\n", i / r->size);
+ else
+ printf(")\n");
+ }
+ }
+
+ if (what & 0x02) {
+ printf(" PCI registers:\n");
+ for (r = schizo_pbm_regnames; r->size != 0; ++r)
+ for (i = 0; i <= r->n_reg; i += r->size) {
+ if ((!sc->sc_tomatillo &&
+ !(r->type & REG_TYPE_SCHIZO)) ||
+ (sc->sc_tomatillo &&
+ !(r->type & REG_TYPE_TOMATILLO)))
+ continue;
+ if ((pbm->sp_bus_a &&
+ !(r->type & REG_TYPE_LEAF_A)) ||
+ (!pbm->sp_bus_a &&
+ !(r->type & REG_TYPE_LEAF_B)))
+ continue;
+ reg = schizo_pbm_read(pbm, r->offset + i);
+ printf("0x%06" PRIx64 " = 0x%016" PRIx64 ""
+ " (%s", r->offset + i, reg, r->name);
+ if (r->n_reg)
+ printf(" %d)\n", i / r->size);
+ else
+ printf(")\n");
+ }
+ }
+
+ if (what & 0x04 && sc->sc_tomatillo) {
+ printf(" Scratch pad registers:\n");
+ for (r = tomatillo_scratch_regnames; r->size != 0; ++r)
+ for (i = 0; i <= r->n_reg; i += r->size) {
+ reg = schizo_pbm_read(pbm, r->offset + i);
+ printf("0x%06" PRIx64 " = 0x%016" PRIx64 ""
+ " (%s", r->offset + i, reg, r->name);
+ if (r->n_reg)
+ printf(" %d)\n", i / r->size);
+ else
+ printf(")\n");
+ }
+ }
+
+ if (what & 0x08) {
+ printf(" IOMMU registers:\n");
+ for (r = schizo_iommu_regnames; r->size != 0; ++r)
+ for (i = 0; i <= r->n_reg; i += r->size) {
+ if ((!sc->sc_tomatillo &&
+ !(r->type & REG_TYPE_SCHIZO)) ||
+ (sc->sc_tomatillo &&
+ !(r->type & REG_TYPE_TOMATILLO)))
+ continue;
+ reg = schizo_pbm_read(pbm, r->offset + i);
+ printf("0x%06" PRIx64 " = 0x%016" PRIx64 ""
+ " (%s", r->offset + i, reg, r->name);
+ if (r->n_reg)
+ printf(" %d)\n", i / r->size);
+ else
+ printf(")\n");
+ }
+ }
+
+ if (what & 0x10 && !sc->sc_tomatillo) {
+ printf(" Streaming cache registers:\n");
+ for (r = schizo_stream_regnames; r->size != 0; ++r)
+ for (i = 0; i <= r->n_reg; i += r->size) {
+ reg = schizo_pbm_read(pbm, r->offset + i);
+ printf("0x%06" PRIx64 " = 0x%016" PRIx64 ""
+ " (%s", r->offset + i, reg, r->name);
+ if (r->n_reg)
+ printf(" %d)\n", i / r->size);
+ else
+ printf(")\n");
+ }
+ }
+
+ if (what & 0x20) {
+ printf(" Interrupt registers:\n");
+ for (r = schizo_intr_regnames; r->size != 0; ++r)
+ for (i = 0; i <= r->n_reg; i += r->size) {
+ if ((!sc->sc_tomatillo &&
+ !(r->type & REG_TYPE_SCHIZO)) ||
+ (sc->sc_tomatillo &&
+ !(r->type & REG_TYPE_TOMATILLO)))
+ continue;
+ reg = schizo_pbm_readintr(pbm, r->offset + i);
+ printf("0x%06" PRIx64 " = 0x%016" PRIx64 ""
+ " (%s", r->offset + i, reg, r->name);
+ if (r->n_reg)
+ printf(" %d)\n", i / r->size);
+ else
+ printf(")\n");
+ }
+ }
+
+ if (what & 0x40 && sc->sc_tomatillo) {
+ printf(" I-chip registers:\n");
+ for (r = tomatillo_ichip_regnames; r->size != 0; ++r)
+ for (i = 0; i <= r->n_reg; i += r->size) {
+ if ((sc->sc_tomatillo &&
+ !(r->type & REG_TYPE_TOMATILLO)))
+ continue;
+ reg = tomatillo_pbm_readichip(pbm,
+ r->offset + i);
+ printf("0x%06" PRIx64 " = 0x%016" PRIx64 ""
+ " (%s", r->offset + i, reg, r->name);
+ if (r->n_reg)
+ printf(" %d)\n", i / r->size);
+ else
+ printf(")\n");
+ }
+ }
+}
+#endif
Index: src/sys/arch/sparc64/dev/schizoreg.h
diff -u src/sys/arch/sparc64/dev/schizoreg.h:1.9 src/sys/arch/sparc64/dev/schizoreg.h:1.9.14.1
--- src/sys/arch/sparc64/dev/schizoreg.h:1.9 Sun Mar 25 03:13:08 2012
+++ src/sys/arch/sparc64/dev/schizoreg.h Tue Jan 26 01:25:32 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: schizoreg.h,v 1.9 2012/03/25 03:13:08 mrg Exp $ */
+/* $NetBSD: schizoreg.h,v 1.9.14.1 2016/01/26 01:25:32 riz Exp $ */
/* $OpenBSD: schizoreg.h,v 1.20 2008/07/12 13:08:04 kettenis Exp $ */
/*
@@ -32,15 +32,25 @@ struct schizo_pbm_regs {
volatile u_int64_t _unused1[64]; /* 0x0000 - 0x01ff */
struct iommureg2 iommu; /* 0x0200 - 0x03ff */
volatile u_int64_t _unused2[384];
- volatile u_int64_t imap[64];
+ volatile u_int64_t imap[64]; /* 0x1000 - 0x11ff */
volatile u_int64_t _unused3[64];
- volatile u_int64_t iclr[64];
- volatile u_int64_t _unused4[320];
+ volatile u_int64_t iclr[64]; /* 0x1400 - 0x15ff */
+ volatile u_int64_t _unused4_0[64];
+ volatile u_int64_t _unused4_1[64]; /* 0x1800 - 0x19ff */
+ volatile u_int64_t intr_retry; /* 0x1a00 */
+ volatile u_int64_t _unused4_2;
+ volatile u_int64_t dma_flushsync_compl; /* 0x1a10 */
+ volatile u_int64_t dma_flushsync_pend; /* 0x1a18 */
+ volatile u_int64_t _unused4_3[60];
+ volatile u_int64_t _unused4_4[64];
+ volatile u_int64_t _unused4_5[64];
volatile u_int64_t ctrl;
volatile u_int64_t __unused0;
volatile u_int64_t afsr;
volatile u_int64_t afar;
- volatile u_int64_t _unused5[252];
+ volatile u_int64_t _unused11[68];
+ volatile u_int64_t int_routing;
+ volatile u_int64_t _unused5[183];
struct iommu_strbuf strbuf;
volatile u_int64_t strbuf_ctxflush;
volatile u_int64_t _unused6[4012];
@@ -112,6 +122,8 @@ struct schizo_regs {
#define SCZ_PCI_ICLR_BASE 0x01400
#define SCZ_PCI_INTR_RETRY 0x01a00 /* interrupt retry */
#define SCZ_PCI_DMA_FLUSH 0x01a08 /* pci consistent dma flush */
+#define TOM_PCI_DMA_FLUSH_COMPLETE 0x01a10 /* diag */
+#define TOM_PCI_DMA_FLUSH_PENDING 0x01a18 /* Tomatillo version */
#define SCZ_PCI_CTRL 0x02000
#define SCZ_PCI_AFSR 0x02010
#define SCZ_PCI_AFAR 0x02018
@@ -298,3 +310,167 @@ struct schizo_range {
u_int32_t size_hi;
u_int32_t size_lo;
};
+
+#ifdef DEBUG
+/*
+ * Register information from:
+ * Schizo Programmer's Reference Manual, September 30, 2007
+ * JIO JBUS to PCI Bridge ASIC, 20 July, 2007
+ *
+ * Some registers are write-only (WO), or can only be accessed when
+ * diagnostics mode is set up (Diag).
+ */
+struct schizo_regname {
+ const u_int64_t offset;
+ const int size;
+ const int n_reg;
+#define REG_TYPE_SCHIZO 0x0001
+#define REG_TYPE_TOMATILLO 0x0002
+#define REG_TYPE_LEAF_A 0x0100
+#define REG_TYPE_LEAF_B 0x0200
+ const int type;
+ const char * name;
+};
+
+/* 0x01 */
+static const struct schizo_regname schizo_regnames[] = {
+ { 0x000000, 8, 0, 1, "UPA0 Address Match Register" },
+ { 0x000000, 8, 0, 2, "UPA0 Offset Base Register" },
+ { 0x000008, 8, 0, 1, "UPA0 Address Mask Register" },
+ { 0x000008, 8, 0, 2, "UPA0 Offset Mask Register" },
+ { 0x000010, 8, 0, 1, "UPA1 Address Match Register" },
+ { 0x000010, 8, 0, 2, "UPA1 Offset Base Register" },
+ { 0x000018, 8, 0, 1, "UPA1 Address Mask Register" },
+ { 0x000018, 8, 0, 2, "UPA1 Offset Mask Register" },
+ { 0x000020, 8, 0, 2, "NewLink Address Match Register" },
+ { 0x000028, 8, 0, 2, "NewLink Address Mask Register" },
+ { 0x000030, 8, 0, 2, "NewLinkAlt Address Match Register" },
+ { 0x000038, 8, 0, 2, "NewLinkAlt Address Mask Register" },
+ { 0x000040, 8, 0, 1, "PCI-A Mem Address Match Register" },
+ { 0x000040, 8, 0, 2, "PCI-A Mem Offset Base Register" },
+ { 0x000048, 8, 0, 1, "PCI-A Mem Address Mask Register" },
+ { 0x000048, 8, 0, 2, "PCI-A Mem Offset Mask Register" },
+ { 0x000050, 8, 0, 1, "PCI-A Cfg IO Address Match Register" },
+ { 0x000050, 8, 0, 2, "PCI-A Cfg IO Offset Base Register" },
+ { 0x000058, 8, 0, 1, "PCI-A Cfg IO Address Mask Register" },
+ { 0x000058, 8, 0, 2, "PCI-A Cfg IO Offset Mask Register" },
+ { 0x000060, 8, 0, 1, "PCI-B Mem Address Match Register" },
+ { 0x000060, 8, 0, 2, "PCI-B Mem Offset Base Register" },
+ { 0x000068, 8, 0, 1, "PCI-B Mem Address Mask Register" },
+ { 0x000068, 8, 0, 2, "PCI-B Mem Offset Mask Register" },
+ { 0x000070, 8, 0, 1, "PCI-B Cfg IO Address Match Register" },
+ { 0x000070, 8, 0, 2, "PCI-B Cfg IO Offset Base Register" },
+ { 0x000078, 8, 0, 1, "PCI-B Cfg IO Address Mask Register" },
+ { 0x000078, 8, 0, 2, "PCI-B Cfg IO Offset Mask Register" },
+ { 0x010000, 8, 0, 3, "Control/Status Register" },
+ { 0x010008, 8, 0, 3, "Error Control Register" },
+ { 0x010010, 8, 0, 3, "Interrupt Control Register" },
+ { 0x010018, 8, 0, 3, "Error Log Register" },
+ { 0x010020, 8, 0, 1, "ECC Control Register" },
+ { 0x010020, 8, 0, 2, "Jbus Parity Control Register" },
+ { 0x010030, 8, 0, 3, "UE AFSR" },
+ { 0x010038, 8, 0, 3, "UE AFAR" },
+ { 0x010040, 8, 0, 3, "CE AFSR" },
+ { 0x010048, 8, 0, 3, "CE AFAR" },
+ { 0x010050, 8, 0, 3, "Energy Star Control Register" },
+ { 0x010058, 8, 0, 1, "Safari Soft Pause Register" },
+ { 0x010058, 8, 0, 2, "Jbus Change Initiation Register" },
+ { 0x011000, 8, 0, 3, "Queue Control Register" },
+ { 0x012000, 8, 0x70, 3, "DTag Diagnostic Register" },
+ { 0x013000, 8, 0x70, 3, "CTag Diagnostic Register" },
+ { 0x014000, 8, 0x18, 3, "Safari Debug Register" },
+ { 0x017000, 8, 0, 3, "Performance Control Register" },
+ { 0x017008, 8, 0, 3, "Performance Counter Register" },
+ { 0x017010, 8, 0, 2, "Reset_Gen Register" },
+ { 0x017018, 8, 0, 2, "Reset_Source Register" },
+ { 0x017020, 8, 0, 2, "UPA Reset Control Register" },
+ { 0x060000, 1, 0, 2, "GPIO 0 Register" },
+ { 0x060001, 1, 0, 2, "GPIO 1 Register" },
+ { 0x062000, 1, 0, 2, "GPIO 2 Register" },
+ { 0x062001, 1, 0, 2, "GPIO 3 Register" },
+ { 0x064000, 8, 0, 2, "GPIO Data Register" },
+ { 0x064008, 8, 0, 2, "GPIO Control Register" },
+ { 0, 0, 0, 0, NULL }
+};
+
+/* 0x02 */
+static const struct schizo_regname schizo_pbm_regnames[] = {
+ { 0x000100, 8, 0, 0x0102, "PCI Performance Monitor Control Register" },
+ { 0x000108, 8, 0, 0x0102, "PCI Performance Counter Register" },
+ { 0x000110, 8, 0, 0x0102, "PCI Idle Check Diagnostics Register" },
+ { 0x002000, 8, 0, 0x0303, "PCI Control/Status Register" },
+ { 0x002010, 8, 0, 0x0303, "PCI AFSR" },
+ { 0x002018, 8, 0, 0x0303, "PCI AFAR" },
+ { 0x002020, 8, 0, 0x0303, "PCI Diagnostic Register" },
+ { 0x002028, 8, 0, 0x0303, "PCI Energy Star Register" },
+ { 0x002030, 8, 0, 0x0302, "PCI Target Retry Limit" },
+ { 0x002038, 8, 0, 0x0302, "PCI Target Latency Timer" },
+ /* See tomatillo_scratch_regnames[] */
+ { 0x002240, 8, 0, 0x0102, "Interrupt Routing Register" },
+ { 0x002490, 8, 0, 0x0302, "PCI Target Address Space Register" },
+ { 0x002498, 8, 0, 0x0302, "PCI Target Error VA Log Register" },
+ { 0, 0, 0, 0, NULL }
+};
+
+/* 0x04 */
+static const struct schizo_regname tomatillo_scratch_regnames[] = {
+ { 0x002040, 8, 0x1f8, 2, "Scratch Pad Register" },
+ { 0, 0, 0, 0, NULL }
+};
+
+/* 0x08 */
+static const struct schizo_regname schizo_iommu_regnames[] = {
+ { 0x000200, 8, 0, 3, "IOMMU Control Register" },
+ { 0x000208, 8, 0, 3, "TSB Base Address Reg" },
+/* WO { 0x000210, 8, 0, 3, "IOMMU Flush Page Register" }, */
+/* WO { 0x000218, 8, 0, 3, "IOMMU Flush Context Register" }, */
+ { 0x000220, 8, 0, 2, "Translation Fault Address Register" },
+ { 0x00a400, 8, 0, 1, "TLB Compare Setup Diag Reg" },
+ { 0x00a408, 8, 0, 1, "TLB Compare Result Diag Reg" },
+/* Diag { 0x00a500, 8, 0x7f, 1, "IOMMU LRU Queue Diag Reg" }, */
+/* Diag { 0x00a580, 8, 0x7f, 1, "TLB Tag Diag Reg" }, */
+/* Diag { 0x00a600, 8, 0x7f, 1, "TLB Data RAM Diag Reg" }, */
+ { 0, 0, 0, 0, NULL }
+};
+
+/* 0x10 */
+static const struct schizo_regname schizo_stream_regnames[] = {
+ { 0x002800, 8, 0, 1, "Streaming Cache Control Reg" },
+/* WO { 0x002808, 8, 0, 1, "Streaming Cache Page Flush/Invalidate Reg" }, */
+/* WO { 0x002810, 8, 0, 1, "Streaming Cache Flush Synchronization Reg" }, */
+/* WO { 0x002818, 8, 0, 1, "Streaming Cache Context Flush/Invalidate Reg" }, */
+ { 0x00b000, 8, 0x7ff, 1, "Streaming Cache Data RAM Diagnostic" },
+/* Diag { 0x00b800, 8, 0x7ff, 1, "Streaming Cache Error Status Diagnostic" }, */
+ { 0x00ba00, 8, 0x7f, 1, "Streaming Cache Page Tag Diagnostic" },
+ { 0x00bb00, 8, 0x7f, 1, "Streaming Cache Line Tag Diagnostic" },
+ { 0x010000, 8, 0x7fff, 1, "Streaming Cache Context Match Reg" },
+ { 0, 0, 0, 0, NULL }
+};
+
+/* 0x20 */
+static const struct schizo_regname schizo_intr_regnames[] = {
+ { 0x001000, 8, 0x1ff, 3, "Interrupt Mapping Register for interrupt INO" },
+ { 0x001400, 8, 0x1ff, 3, "Clear Interrupt Register for interrupt INO" },
+ { 0x001a00, 8, 0, 3, "Interrupt Retry Register" },
+ { 0x001a08, 8, 0, 3, "PCI Consistent DMA Flush/Sync Register" },
+ { 0x006000, 8, 0, 3, "UPA Port 0 Interrupt Mapping Register" },
+ { 0x008000, 8, 0, 3, "UPA Port 1 Interrupt Mapping Register" },
+ { 0x00a800, 8, 0, 3, "PCI Int State Diag Register" },
+ { 0x00a808, 8, 0, 3, "OBIO and Internal Int State Diag Register" },
+ { 0, 0, 0, 0, NULL }
+};
+
+/* 0x40 */
+static const struct schizo_regname tomatillo_ichip_regnames[] = {
+ { 0x001000, 8, 0x1ff, 3, "Interrupt Mapping Register for interrupt INO" },
+ { 0x001400, 8, 0x1ff, 3, "Clear Interrupt Register for interrupt INO" },
+ { 0x001a00, 8, 0, 3, "Interrupt Retry Register" },
+ { 0x001a10, 8, 0, 3, "I-chip DMA Flush/Sync Complete Register" },
+ { 0x001a18, 8, 0, 3, "I-chip DMA Flush/Sync Pending Register" },
+ { 0x006000, 8, 0, 3, "UPA Port 0 Interrupt Mapping Register" },
+ { 0x008000, 8, 0, 3, "UPA Port 1 Interrupt Mapping Register" },
+ { 0x00a800, 8, 0, 3, "PCI Int State Diag Register" },
+ { 0x00a808, 8, 0, 3, "OBIO and Internal Int State Diag Register" },
+ { 0, 0, 0, 0, NULL }
+};
+#endif
Index: src/sys/arch/sparc64/dev/schizovar.h
diff -u src/sys/arch/sparc64/dev/schizovar.h:1.6 src/sys/arch/sparc64/dev/schizovar.h:1.6.14.1
--- src/sys/arch/sparc64/dev/schizovar.h:1.6 Sun Mar 25 03:13:08 2012
+++ src/sys/arch/sparc64/dev/schizovar.h Tue Jan 26 01:25:32 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: schizovar.h,v 1.6 2012/03/25 03:13:08 mrg Exp $ */
+/* $NetBSD: schizovar.h,v 1.6.14.1 2016/01/26 01:25:32 riz Exp $ */
/* $OpenBSD: schizovar.h,v 1.10 2007/01/14 16:19:49 kettenis Exp $ */
/*
@@ -50,6 +50,9 @@ struct schizo_pbm {
struct iommu_state sp_is;
struct strbuf_ctl sp_sb;
char sp_flush[0x80];
+#ifdef DEBUG
+ bus_space_handle_t sp_ichiph;
+#endif
};
struct schizo_softc {
@@ -64,6 +67,9 @@ struct schizo_softc {
int sc_busa;
int sc_tomatillo;
uint32_t sc_ver;
+#ifdef DEBUG
+ struct schizo_pbm* sc_pbm;
+#endif
};
#define schizo_read(sc,r) \
@@ -82,3 +88,9 @@ struct schizo_softc {
bus_space_read_4((pbm)->sp_cfgt, (pbm)->sp_cfgh, (r))
#define schizo_cfg_write(pbm,r,v) \
bus_space_write_4((pbm)->sp_cfgt, (pbm)->sp_cfgh, (r), (v))
+#ifdef DEBUG
+#define schizo_read_1(sc,r) \
+ bus_space_read_1((sc)->sc_bustag, (sc)->sc_ctrlh, (r))
+#define tomatillo_pbm_readichip(pbm,r) \
+ bus_space_read_8((pbm)->sp_regt, (pbm)->sp_ichiph, (r))
+#endif
