Module Name: src
Committed By: palle
Date: Wed Feb 3 20:33:52 UTC 2016
Modified Files:
src/sys/arch/sparc64/include: ctlreg.h
src/sys/arch/sparc64/sparc64: locore.s pmap.c
Log Message:
sun4v: extend dmmu_set_secondary_context() to handle both sun4u and sun4v. ok
martin@
To generate a diff of this commit:
cvs rdiff -u -r1.62 -r1.63 src/sys/arch/sparc64/include/ctlreg.h
cvs rdiff -u -r1.386 -r1.387 src/sys/arch/sparc64/sparc64/locore.s
cvs rdiff -u -r1.300 -r1.301 src/sys/arch/sparc64/sparc64/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/include/ctlreg.h
diff -u src/sys/arch/sparc64/include/ctlreg.h:1.62 src/sys/arch/sparc64/include/ctlreg.h:1.63
--- src/sys/arch/sparc64/include/ctlreg.h:1.62 Wed Apr 1 18:38:30 2015
+++ src/sys/arch/sparc64/include/ctlreg.h Wed Feb 3 20:33:52 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ctlreg.h,v 1.62 2015/04/01 18:38:30 palle Exp $ */
+/* $NetBSD: ctlreg.h,v 1.63 2016/02/03 20:33:52 palle Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
@@ -55,7 +55,7 @@
#define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */
#define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */
-#define ASI_MMU 0x21 /* [4v] MMU context control - both IMMU and DMMU */
+#define ASI_MMU_CONTEXTID 0x21 /* [4v] MMU context control - both IMMU and DMMU */
#define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */
#define ASI_QUEUE 0x25 /* [4v] interrupt queue registers */
@@ -864,16 +864,6 @@ SPARC64_ST_DEF(sta, uint32_t)
SPARC64_ST_DEF64(stxa, uint64_t)
-/* set dmmu secondary context */
-static __inline void
-dmmu_set_secondary_context(uint ctx)
-{
- __asm volatile(
- "stxa %0,[%1]%2; "
- "membar #Sync "
- : : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_DMMU)
- : "memory");
-}
/* flush address from data cache */
#define flush(loc) __asm volatile("flush %0" : : "r" ((__uintptr_t)(loc)))
Index: src/sys/arch/sparc64/sparc64/locore.s
diff -u src/sys/arch/sparc64/sparc64/locore.s:1.386 src/sys/arch/sparc64/sparc64/locore.s:1.387
--- src/sys/arch/sparc64/sparc64/locore.s:1.386 Fri Nov 6 15:30:59 2015
+++ src/sys/arch/sparc64/sparc64/locore.s Wed Feb 3 20:33:52 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.386 2015/11/06 15:30:59 martin Exp $ */
+/* $NetBSD: locore.s,v 1.387 2016/02/03 20:33:52 palle Exp $ */
/*
* Copyright (c) 2006-2010 Matthew R. Green
@@ -129,7 +129,7 @@
#ifdef SUN4V
.macro SET_MMU_CONTEXTID_SUN4V ctxid,ctx
- stxa \ctxid, [\ctx] ASI_MMU;
+ stxa \ctxid, [\ctx] ASI_MMU_CONTEXTID;
.endm
#endif
Index: src/sys/arch/sparc64/sparc64/pmap.c
diff -u src/sys/arch/sparc64/sparc64/pmap.c:1.300 src/sys/arch/sparc64/sparc64/pmap.c:1.301
--- src/sys/arch/sparc64/sparc64/pmap.c:1.300 Fri Nov 27 13:51:24 2015
+++ src/sys/arch/sparc64/sparc64/pmap.c Wed Feb 3 20:33:52 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.300 2015/11/27 13:51:24 joerg Exp $ */
+/* $NetBSD: pmap.c,v 1.301 2016/02/03 20:33:52 palle Exp $ */
/*
*
* Copyright (C) 1996-1999 Eduardo Horvath.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.300 2015/11/27 13:51:24 joerg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.301 2016/02/03 20:33:52 palle Exp $");
#undef NO_VCACHE /* Don't forget the locked TLB in dostart */
#define HWREF
@@ -158,6 +158,25 @@ static bool pmap_is_referenced_locked(st
static void ctx_free(struct pmap *, struct cpu_info *);
+/* set dmmu secondary context */
+static __inline void
+dmmu_set_secondary_context(uint ctx)
+{
+ if (!CPU_ISSUN4V)
+ __asm volatile(
+ "stxa %0,[%1]%2; "
+ "membar #Sync "
+ : : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_DMMU)
+ : "memory");
+ else
+ __asm volatile(
+ "stxa %0,[%1]%2; "
+ "membar #Sync "
+ : : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_MMU_CONTEXTID)
+ : "memory");
+
+}
+
/*
* Check if any MMU has a non-zero context
*/
