Module Name: src
Committed By: martin
Date: Sun Mar 6 17:49:56 UTC 2016
Modified Files:
src/sys/arch/x86/include [netbsd-7]: cacheinfo.h specialreg.h
src/usr.sbin/cpuctl/arch [netbsd-7]: i386.c
Log Message:
Pull up the following changes, requested by msaitoh in #1117:
sys/arch/x86/include/cacheinfo.h 1.20-1.21
sys/arch/x86/include/specialreg.h 1.83-1.86
usr.sbin/cpuctl/arch/i386.c 1.67-1.70
Changes for x86's cpuctl(8):
- Add some TLB information (index 0x6a-0x6d).
- Add Hardware-Controlled Performance States (HWP) bits, FPU Data
Pointer Updated Only bit and CLFLUSHOPT bit.
- Add some AMD's bit definitions from "BIOS and Kernel Developer(BKDG)
for AMD Family 15h Models 60h-6Fh Processors".
- Add Xeon E5-4600 v3,
- Add Xeon E3-1200 v4 and v5.
- Add 6th gen Core, Xeon E3-1500 v5 and Xeon D-1500.
- Change CPU family 0x1c from "Atom Family" to "45nm Atom Family"
To generate a diff of this commit:
cvs rdiff -u -r1.18.2.1 -r1.18.2.2 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -u -r1.78.4.3 -r1.78.4.4 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.58.2.4 -r1.58.2.5 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.18.2.1 src/sys/arch/x86/include/cacheinfo.h:1.18.2.2
--- src/sys/arch/x86/include/cacheinfo.h:1.18.2.1 Fri Dec 12 16:44:35 2014
+++ src/sys/arch/x86/include/cacheinfo.h Sun Mar 6 17:49:55 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.18.2.1 2014/12/12 16:44:35 martin Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.18.2.2 2016/03/06 17:49:55 martin Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -234,6 +234,10 @@ __CI_TBL(CAI_DTLB, 0x5c, 0xff, 64,
__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
__CI_TBL(CAI_ITLB, 0x61, 0xff, 48, 4 * 1024, NULL), \
__CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \
+__CI_TBL(CAI_ITLB, 0x6a, 8, 64, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0x6b, 8,256, 4 * 1024, NULL), \
+__CI_TBL(CAI_L2_DTLB2, 0x6c, 8,128, 0, "2M/4M: 128 entries"),\
+__CI_TBL(CAI_L1_1GBDTLB,0x6d,0xff, 16,1024*1024 * 1024, NULL), \
__CI_TBL(CAI_ITLB2, 0x76, 0xff, 8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \
__CI_TBL(CAI_DTLB, 0xa0, 0xff, 32, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL), \
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.78.4.3 src/sys/arch/x86/include/specialreg.h:1.78.4.4
--- src/sys/arch/x86/include/specialreg.h:1.78.4.3 Sat May 9 08:35:10 2015
+++ src/sys/arch/x86/include/specialreg.h Sun Mar 6 17:49:55 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.78.4.3 2015/05/09 08:35:10 snj Exp $ */
+/* $NetBSD: specialreg.h,v 1.78.4.4 2016/03/06 17:49:55 martin Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -279,16 +279,24 @@
* Intel Digital Thermal Sensor and
* Power Management, Fn0000_0006 - %eax.
*/
-#define CPUID_DSPM_DTS 0x00000001 /* Digital Thermal Sensor */
-#define CPUID_DSPM_IDA 0x00000002 /* Intel Dynamic Acceleration */
-#define CPUID_DSPM_ARAT 0x00000004 /* Always Running APIC Timer */
-#define CPUID_DSPM_PLN 0x00000010 /* Power Limit Notification */
-#define CPUID_DSPM_CME 0x00000020 /* Clock Modulation Extension */
-#define CPUID_DSPM_PLTM 0x00000040 /* Package Level Thermal Management */
+#define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */
+#define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */
+#define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */
+#define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */
+#define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */
+#define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */
+#define CPUID_DSPM_HWP __BIT(7) /* HWP */
+#define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */
+#define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */
+#define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */
+#define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */
+#define CPUID_DSPM_HDC __BIT(13) /* HDC */
#define CPUID_DSPM_FLAGS "\20" \
- "\1" "DTS" "\2" "IDA" "\3" "ARAT" \
- "\5" "PLN" "\6" "CME" "\7" "PLTM"
+ "\1" "DTS" "\2" "IDA" "\3" "ARAT" \
+ "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \
+ "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \
+ "\16" "HDC"
/*
* Intel Digital Thermal Sensor and
@@ -313,6 +321,7 @@
#define CPUID_SEF_BMI1 __BIT(3)
#define CPUID_SEF_HLE __BIT(4)
#define CPUID_SEF_AVX2 __BIT(5)
+#define CPUID_SEF_FDPEXONLY __BIT(6)
#define CPUID_SEF_SMEP __BIT(7)
#define CPUID_SEF_BMI2 __BIT(8)
#define CPUID_SEF_ERMS __BIT(9)
@@ -326,6 +335,7 @@
#define CPUID_SEF_RDSEED __BIT(18)
#define CPUID_SEF_ADX __BIT(19)
#define CPUID_SEF_SMAP __BIT(20)
+#define CPUID_SEF_CLFLUSHOPT __BIT(23)
#define CPUID_SEF_PT __BIT(25)
#define CPUID_SEF_AVX512PF __BIT(26)
#define CPUID_SEF_AVX512ER __BIT(27)
@@ -334,12 +344,12 @@
#define CPUID_SEF_FLAGS "\20" \
"\1" "FSGSBASE" "\2" "TSCADJUST" "\4" "BMI1" \
- "\5" "HLE" "\6" "AVX2" "\10" "SMEP" \
+ "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \
"\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \
"\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \
"\21" "AVX512F" "\23" "RDSEED" "\24" "ADX" \
- "\25" "SMAP" \
- "\32" "PT" "\33" "AVX512PF""\34" "AVX512ER"\
+ "\25" "SMAP" "\26" "CLFLUSHOPT" \
+ "\32" "PT" "\33" "AVX512PF""\34" "AVX512ER" \
"\35" "AVX512CD""\36" "SHA"
/* %ecx */
@@ -437,6 +447,7 @@
#define CPUID_WDT 0x00002000 /* watchdog timer support */
#define CPUID_LWP 0x00008000 /* Light Weight Profiling */
#define CPUID_FMA4 0x00010000 /* FMA4 instructions */
+#define CPUID_TCE 0x00020000 /* Translation cache Extension */
#define CPUID_NODEID 0x00080000 /* NodeID MSR available*/
#define CPUID_TBM 0x00200000 /* TBM instructions */
#define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */
@@ -445,6 +456,8 @@
#define CPUID_SPM 0x02000000 /* Stream Perf Mon */
#define CPUID_DBE 0x04000000 /* Data Breakpoint Extension */
#define CPUID_PTSC 0x08000000 /* PerfTsc */
+#define CPUID_L2IPERFC 0x10000000 /* L2I performance counter Extension */
+#define CPUID_MWAITX 0x20000000 /* MWAITX/MONITORX support */
#define CPUID_AMD_FLAGS4 "\20" \
"\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \
@@ -452,10 +465,10 @@
"\11" "3DNOWPREFETCH" \
"\12" "OSVW" "\13" "IBS" "\14" "XOP" \
"\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \
- "\21" "FMA4" "\22" "B17" "\23" "B18" "\24" "NodeID" \
+ "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \
"\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \
"\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \
- "\35" "B28" "\36" "B29" "\37" "B30" "\40" "B31"
+ "\35" "L2IPERFC" "\36" "MWAITX" "\37" "B30" "\40" "B31"
/*
* AMD Advanced Power Management
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.58.2.4 src/usr.sbin/cpuctl/arch/i386.c:1.58.2.5
--- src/usr.sbin/cpuctl/arch/i386.c:1.58.2.4 Sat May 9 08:35:10 2015
+++ src/usr.sbin/cpuctl/arch/i386.c Sun Mar 6 17:49:56 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.58.2.4 2015/05/09 08:35:10 snj Exp $ */
+/* $NetBSD: i386.c,v 1.58.2.5 2016/03/06 17:49:56 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.58.2.4 2015/05/09 08:35:10 snj Exp $");
+__RCSID("$NetBSD: i386.c,v 1.58.2.5 2016/03/06 17:49:56 martin Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -333,7 +333,7 @@ const struct cpu_cpuid_nameclass i386_cp
"Core 2 Quad 8xxx and 9xxx",
[0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx "
"(Nehalem)",
- [0x1c] = "Atom Family",
+ [0x1c] = "45nm Atom Family",
[0x1d] = "XeonMP 74xx (Nehalem)",
[0x1e] = "Core i7 and i5",
[0x1f] = "Core i7 and i5",
@@ -354,26 +354,26 @@ const struct cpu_cpuid_nameclass i386_cp
"Ivy Bridge",
[0x3c] = "4th gen Core, Xeon E3-12xx v3 "
"(Haswell)",
- [0x3d] = "Core M-5xxx, Future 5th gen Core (Broadwell)",
+ [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)",
[0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), "
"Core i7-49xx Extreme",
- [0x3f] = "Xeon E5-2600/1600 v3 (Haswell-E), "
+ [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), "
"Core i7-59xx Extreme",
[0x45] = "4th gen Core, Xeon E3-12xx v3 "
"(Haswell)",
[0x46] = "4th gen Core, Xeon E3-12xx v3 "
"(Haswell)",
- [0x47] = "5th gen Core (Broadwell)",
+ [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)",
[0x4a] = "Atom Z3400",
[0x4c] = "Atom X[57]-Z8000 (Airmont)",
[0x4d] = "Atom C2000",
- [0x4e] = "Next gen Core (Sky Lake)",
+ [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
[0x4f] = "Future gen Xeon (Broadwell)",
- [0x56] = "Next gen Xeon D (Broadwell)",
+ [0x56] = "Xeon D-1500 (Broadwell)",
[0x57] = "Next gen Xeon Phi",
[0x5a] = "Atom E3500",
[0x5d] = "Atom X3-C3000 (Silvermont)",
- [0x5e] = "Next gen Core (Sky Lake)",
+ [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
},
"Pentium Pro, II or III", /* Default */
NULL,
