Module Name: src
Committed By: kiyohara
Date: Sun Jul 3 12:27:04 UTC 2016
Modified Files:
src/sys/arch/arm/omap: omap2_obiovar.h omap2_reg.h omap3_scm.c
Log Message:
Print DeviceID in attach(). Also test OMAP35x/AM37x/DM37x. And add
omap_devid().
Tested on OMAP3503, OMAP3530 and AM3703.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/omap/omap2_obiovar.h \
src/sys/arch/arm/omap/omap3_scm.c
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/omap/omap2_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/omap/omap2_obiovar.h
diff -u src/sys/arch/arm/omap/omap2_obiovar.h:1.4 src/sys/arch/arm/omap/omap2_obiovar.h:1.5
--- src/sys/arch/arm/omap/omap2_obiovar.h:1.4 Mon Apr 25 13:14:37 2016
+++ src/sys/arch/arm/omap/omap2_obiovar.h Sun Jul 3 12:27:04 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: omap2_obiovar.h,v 1.4 2016/04/25 13:14:37 kiyohara Exp $ */
+/* $NetBSD: omap2_obiovar.h,v 1.5 2016/07/03 12:27:04 kiyohara Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -54,5 +54,6 @@ struct obio_softc {
};
uint32_t omap_chipid(void);
+uint32_t omap_devid(void);
#endif /* _ARM_OMAP_OMAP2_OBIOVAR_H_ */
Index: src/sys/arch/arm/omap/omap3_scm.c
diff -u src/sys/arch/arm/omap/omap3_scm.c:1.4 src/sys/arch/arm/omap/omap3_scm.c:1.5
--- src/sys/arch/arm/omap/omap3_scm.c:1.4 Mon Apr 25 13:14:37 2016
+++ src/sys/arch/arm/omap/omap3_scm.c Sun Jul 3 12:27:04 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: omap3_scm.c,v 1.4 2016/04/25 13:14:37 kiyohara Exp $ */
+/* $NetBSD: omap3_scm.c,v 1.5 2016/07/03 12:27:04 kiyohara Exp $ */
/*-
* Copyright (c) 2013 Jared D. McNeill <jmcne...@invisible.ca>
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap3_scm.c,v 1.4 2016/04/25 13:14:37 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap3_scm.c,v 1.5 2016/07/03 12:27:04 kiyohara Exp $");
#include "opt_omap.h"
@@ -47,12 +47,14 @@ __KERNEL_RCSID(0, "$NetBSD: omap3_scm.c,
#define SCM_BASE_3530 0x48002000
#define SCM_SIZE_3530 0x1000
+#define SCM_CONTROL_IDCODE_3530 0x308204
#define SCM_OFFSET_INTERFACE_3530 0
#define SCM_OFFSET_GENERAL_3530 0x270
#if defined(OMAP_3430) || defined(OMAP_3530)
#define SCM_BASE SCM_BASE_3530
#define SCM_SIZE SCM_SIZE_3530
+#define SCM_CONTROL_IDCODE SCM_CONTROL_IDCODE_3530
#define SCM_OFFSET_INTERFACE SCM_OFFSET_INTERFACE_3530
#define SCM_OFFSET_GENERAL SCM_OFFSET_GENERAL_3530
#endif
@@ -105,7 +107,8 @@ struct omap3_scm_softc {
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
- uint32_t sc_cid;
+ uint32_t sc_cid; /* Chip Identification */
+ uint32_t sc_did; /* Device IDCODE */
/* GENERAL */
struct sysmon_envsys *sc_sme;
@@ -143,9 +146,28 @@ omap3_scm_attach(device_t parent, device
{
struct omap3_scm_softc *sc = device_private(self);
struct obio_attach_args *obio = opaque;
+ bus_space_handle_t ioh;
uint32_t rev;
char buf[256];
- const char *cid;
+ const char *cid, *did, *fmt;
+ const char *omap35x_fmt = "\177\020"
+ "b\0TO_OUT\0"
+ "b\1four_bit_mmc\0"
+ "b\2CCP2_CSI1\0"
+ "b\3CMADS_FL3G\0"
+ "b\4NEON_VFPLite\0"
+ "b\5ISP_disable\0"
+ "f\6\2IVA2_MHz\0=\0 430\0=\2 266\0"
+ "f\10\2ARM_MHz\0=\0 600\0=\1 400\0=\2 266\0"
+ "f\12\2MPU_L2_cache_size\0=\0 0KB\0=\1 64KB\0=\2 128KB\0=\3 Full\0"
+ "b\14IVA_disable_acc\0"
+ "f\15\2SGX_scalable_control\0=\0Full\0=\1Half\0=\2not-present\0\0";
+ const char *amdm37x_fmt = "\177\020"
+ "f\0\4Feature Tiering\0=\0All features aval\0=\1ISP not avail\0"
+ "f\11\1MPU/IVA frequency\0=\0 800/600 MHz\0=\1 1000/800 MHz\0"
+ "f\12\2MPU_L2_cache_size\0=\0 0KB\0=\2 128KB\0=\3 Full\0"
+ "f\14\1IVA 2.2 subsystem\0=\0Full use\0=\1Not available\0"
+ "f\15\2 2D/3D accelerator\0=\0Full use\0=\2HW not present\0";
aprint_naive("\n");
@@ -159,32 +181,83 @@ omap3_scm_attach(device_t parent, device
aprint_error(": couldn't map address space\n");
return;
}
+ if (bus_space_map(obio->obio_iot,
+ obio->obio_addr + SCM_CONTROL_IDCODE, sizeof(uint32_t),
+ 0, &ioh) != 0) {
+ aprint_error(": couldn't map CONTROL_IDCODE space\n");
+ return;
+ }
+ sc->sc_did = bus_space_read_4(sc->sc_iot, ioh, 0);
+ bus_space_unmap(sc->sc_iot, ioh, sizeof(uint32_t));
rev = SCM_READ_REG(sc, CONTROL_REVISION);
aprint_normal(": rev. 0x%x\n", rev & 0xff);
sc->sc_cid = SCM_READ_REG(sc, CONTROL_OMAP_STATUS & 0xffff);
- switch (sc->sc_cid) {
- case CHIPID_OMAP3503: cid = "OMAP3503"; break;
- case CHIPID_OMAP3515: cid = "OMAP3515"; break;
- case CHIPID_OMAP3525: cid = "OMAP3525"; break;
- case CHIPID_OMAP3530: cid = "OMAP3530"; break;
- default: cid = "unknwon"; break;
+ cid = did = fmt = NULL;
+ switch (sc->sc_did) {
+ case DEVID_OMAP35X_ES10:
+ case DEVID_OMAP35X_ES20:
+ case DEVID_OMAP35X_ES21:
+ case DEVID_OMAP35X_ES30:
+ case DEVID_OMAP35X_ES31:
+ case DEVID_OMAP35X_ES312:
+ switch (sc->sc_cid) {
+ case CHIPID_OMAP3503: cid = "OMAP3503"; break;
+ case CHIPID_OMAP3515: cid = "OMAP3515"; break;
+ case CHIPID_OMAP3525: cid = "OMAP3525"; break;
+ case CHIPID_OMAP3530: cid = "OMAP3530"; break;
+ }
+ switch (sc->sc_did) {
+ case DEVID_OMAP35X_ES10: did = "ES1.0"; break;
+ case DEVID_OMAP35X_ES20: did = "ES2.0"; break;
+ case DEVID_OMAP35X_ES21: did = "ES2.1"; break;
+ case DEVID_OMAP35X_ES30: did = "ES3.0"; break;
+ case DEVID_OMAP35X_ES31: did = "ES3.1"; break;
+ case DEVID_OMAP35X_ES312: did = "ES3.1.2";break;
+ }
+ fmt = omap35x_fmt;
+ break;
+
+ case DEVID_AMDM37X_ES10:
+ case DEVID_AMDM37X_ES11:
+ case DEVID_AMDM37X_ES12:
+ switch (sc->sc_cid) {
+ case CHIPID_OMAP3503:
+ case CHIPID_AM3703:
+ cid = "AM3703";
+ break;
+ case CHIPID_OMAP3515:
+ case CHIPID_AM3715:
+ cid = "AM3715";
+ break;
+ case CHIPID_OMAP3525:
+ case CHIPID_DM3725:
+ cid = "DM3525";
+ break;
+ case CHIPID_OMAP3530:
+ case CHIPID_DM3730:
+ cid = "DM3730";
+ break;
+ }
+ switch (sc->sc_did) {
+ case DEVID_AMDM37X_ES10: did = "ES1.0"; break;
+ case DEVID_AMDM37X_ES11: did = "ES1.1"; break;
+ case DEVID_AMDM37X_ES12: did = "ES1.2"; break;
+ }
+ fmt = amdm37x_fmt;
+ break;
+ break;
+
+ default:
+ aprint_normal_dev(self,
+ "unknwon ChipID/DeviceID found 0x%08x/0x%08x\n",
+ sc->sc_cid, sc->sc_did);
+ break;
}
- aprint_normal_dev(self, "%s: ", cid);
- snprintb(buf, sizeof(buf), "\177\020"
- "b\0TO_OUT\0"
- "b\1four_bit_mmc\0"
- "b\2CCP2_CSI1\0"
- "b\3CMADS_FL3G\0"
- "b\4NEON_VFPLite\0"
- "b\5ISP_disable\0"
- "f\6\2IVA2_MHz\0=\0 430\0=\2 266\0"
- "f\10\2ARM_MHz\0=\0 600\0=\1 400\0=\2 266\0"
- "f\12\2MPU_L2_cache_size\0=\0 0KB\0=\1 64KB\0=\2 128KB\0=\3 Full\0"
- "b\14IVA_disable_acc\0"
- "f\15\2SGX_scalable_control\0=\0Full\0=\1Half\0=\2not-present\0\0",
- sc->sc_cid);
- aprint_normal("%s\n", buf);
+ if (fmt != NULL)
+ snprintb(buf, sizeof(buf), fmt, sc->sc_cid);
+ if (did != NULL)
+ aprint_normal_dev(self, "%s %s: %s\n", cid, did, buf);
omap3_scm_sensor_attach(sc);
}
@@ -266,3 +339,15 @@ omap_chipid(void)
sc = device_private(dev);
return sc->sc_cid;
}
+
+uint32_t
+omap_devid(void)
+{
+ struct omap3_scm_softc *sc;
+ device_t dev;
+
+ dev = device_find_by_xname("omapscm0");
+ KASSERT(dev != NULL);
+ sc = device_private(dev);
+ return sc->sc_did;
+}
Index: src/sys/arch/arm/omap/omap2_reg.h
diff -u src/sys/arch/arm/omap/omap2_reg.h:1.31 src/sys/arch/arm/omap/omap2_reg.h:1.32
--- src/sys/arch/arm/omap/omap2_reg.h:1.31 Mon Apr 25 13:07:03 2016
+++ src/sys/arch/arm/omap/omap2_reg.h Sun Jul 3 12:27:04 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: omap2_reg.h,v 1.31 2016/04/25 13:07:03 kiyohara Exp $ */
+/* $NetBSD: omap2_reg.h,v 1.32 2016/07/03 12:27:04 kiyohara Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -147,6 +147,22 @@
#define CHIPID_OMAP3525 0x4c00
#define CHIPID_OMAP3530 0x0c00
+#define DEVID_OMAP35X_ES10 0x0b6d602f
+#define DEVID_OMAP35X_ES20 0x1b7ae02f
+#define DEVID_OMAP35X_ES21 0x2b7ae02f
+#define DEVID_OMAP35X_ES30 0x3b7ae02f
+#define DEVID_OMAP35X_ES31 0x4b7ae02f
+#define DEVID_OMAP35X_ES312 0x7b7ae02f
+
+#define CHIPID_AM3703 0x5e00 /* or 0x5c00 */
+#define CHIPID_AM3715 0x1e00 /* or 0x1c00 */
+#define CHIPID_DM3725 0x4e00 /* or 0x4c00 */
+#define CHIPID_DM3730 0x0e00 /* or 0x0c00 */
+
+#define DEVID_AMDM37X_ES10 0x0b89102f
+#define DEVID_AMDM37X_ES11 0x1b89102f
+#define DEVID_AMDM37X_ES12 0x2b89102f
+
/*
* Clock Management registers base, offsets, and size
*/
