CVS commit: src/sys/arch/arm/arm32

[Matt Thomas]

Module Name:    src
Committed By:   matt
Date:           Mon Jul 11 16:09:27 UTC 2016

Modified Files:
        src/sys/arch/arm/arm32: arm32_tlb.c

Log Message:
Adapt to common pmap changes.


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/arm32/arm32_tlb.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/arm/arm32/arm32_tlb.c
diff -u src/sys/arch/arm/arm32/arm32_tlb.c:1.9 src/sys/arch/arm/arm32/arm32_tlb.c:1.10
--- src/sys/arch/arm/arm32/arm32_tlb.c:1.9	Thu Mar 26 08:45:05 2015
+++ src/sys/arch/arm/arm32/arm32_tlb.c	Mon Jul 11 16:09:27 2016
@@ -30,7 +30,7 @@
 #include "opt_multiprocessor.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.9 2015/03/26 08:45:05 hsuenaga Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.10 2016/07/11 16:09:27 matt Exp $");
 
 #include <sys/param.h>
 #include <sys/types.h>
@@ -77,6 +77,7 @@ tlb_invalidate_all(void)
 			armreg_iciallu_write(0);
 		}
 	}
+	arm_dsb();
 	arm_isb();
 }
 
@@ -99,6 +100,7 @@ tlb_invalidate_asids(tlb_asid_t lo, tlb_
 			armreg_tlbiasid_write(lo);
 #endif
 		}
+		arm_dsb();
 		arm_isb();
 		if (__predict_false(vivt_icache_p)) {
 #ifdef MULTIPROCESSOR
@@ -130,7 +132,6 @@ tlb_invalidate_addr(vaddr_t va, tlb_asid
 #endif
 		//armreg_tlbiall_write(asid);
 	}
-	arm_dsb();
 	arm_isb();
 }
 
@@ -143,7 +144,7 @@ tlb_update_addr(vaddr_t va, tlb_asid_t a
 
 #if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA5)
 static u_int
-tlb_cortex_a5_record_asids(u_long *mapp)
+tlb_cortex_a5_record_asids(u_long *mapp, tlb_asid_t asid_max)
 {
 	u_int nasids = 0;
 	for (size_t va_index = 0; va_index < 63; va_index++) {
@@ -175,7 +176,7 @@ tlb_cortex_a5_record_asids(u_long *mapp)
 
 #if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA7)
 static u_int
-tlb_cortex_a7_record_asids(u_long *mapp)
+tlb_cortex_a7_record_asids(u_long *mapp, tlb_asid_t asid_max)
 {
 	u_int nasids = 0;
 	for (size_t va_index = 0; va_index < 128; va_index++) {
@@ -207,16 +208,16 @@ tlb_cortex_a7_record_asids(u_long *mapp)
 #endif
 
 u_int
-tlb_record_asids(u_long *mapp)
+tlb_record_asids(u_long *mapp, tlb_asid_t asid_max)
 {
 #ifndef MULTIPROCESSOR
 #ifdef CPU_CORTEXA5
 	if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid))
-		return tlb_cortex_a5_record_asids(mapp);
+		return tlb_cortex_a5_record_asids(mapp, asid_max);
 #endif
 #ifdef CPU_CORTEXA7
 	if (CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid))
-		return tlb_cortex_a7_record_asids(mapp);
+		return tlb_cortex_a7_record_asids(mapp, asid_max);
 #endif
 #endif /* MULTIPROCESSOR */
 #ifdef DIAGNOSTIC