Module Name: src
Committed By: matt
Date: Mon Jul 11 23:06:54 UTC 2016
Modified Files:
src/sys/arch/mips/conf: files.mips
src/sys/arch/mips/include: cache_r4k.h
src/sys/arch/mips/mips: cache.c cache_r4k.c
Log Message:
Use sdcache routines.
Remove old cache support.
Switch to new cache routines.
To generate a diff of this commit:
cvs rdiff -u -r1.74 -r1.75 src/sys/arch/mips/conf/files.mips
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/mips/include/cache_r4k.h
cvs rdiff -u -r1.51 -r1.52 src/sys/arch/mips/mips/cache.c
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/mips/mips/cache_r4k.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/conf/files.mips
diff -u src/sys/arch/mips/conf/files.mips:1.74 src/sys/arch/mips/conf/files.mips:1.75
--- src/sys/arch/mips/conf/files.mips:1.74 Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/conf/files.mips Mon Jul 11 23:06:53 2016
@@ -1,4 +1,4 @@
-# $NetBSD: files.mips,v 1.74 2016/07/11 16:15:35 matt Exp $
+# $NetBSD: files.mips,v 1.75 2016/07/11 23:06:53 matt Exp $
#
defflag opt_cputype.h NOFPU FPEMUL
@@ -77,12 +77,12 @@ file arch/mips/mips/cache_octeon.c mips
file arch/mips/mips/cache_mipsNN.c mips32|mips32r2|mips64|mips64r2
file arch/mips/mips/cache_r4k_pcache16.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
file arch/mips/mips/cache_r4k_pcache32.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
-file arch/mips/mips/cache_r4k_pcache64.S mips32|mips32r2|mips64|mips64r2
-file arch/mips/mips/cache_r4k_pcache128.S mips32|mips32r2|mips64|mips64r2
-#file arch/mips/mips/cache_r4k_scache16.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
-#file arch/mips/mips/cache_r4k_scache32.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
-#file arch/mips/mips/cache_r4k_scache64.S mips32|mips32r2|mips64|mips64r2
-#file arch/mips/mips/cache_r4k_scache128.S mips32|mips32r2|mips64|mips64r2
+file arch/mips/mips/cache_r4k_pcache64.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
+file arch/mips/mips/cache_r4k_pcache128.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
+file arch/mips/mips/cache_r4k_scache16.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
+file arch/mips/mips/cache_r4k_scache32.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
+file arch/mips/mips/cache_r4k_scache64.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
+file arch/mips/mips/cache_r4k_scache128.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
file arch/mips/mips/mips_fputrap.c !nofpu | fpemul
file arch/mips/mips/mips_emul.c
Index: src/sys/arch/mips/include/cache_r4k.h
diff -u src/sys/arch/mips/include/cache_r4k.h:1.13 src/sys/arch/mips/include/cache_r4k.h:1.14
--- src/sys/arch/mips/include/cache_r4k.h:1.13 Mon Jul 11 19:06:33 2016
+++ src/sys/arch/mips/include/cache_r4k.h Mon Jul 11 23:06:54 2016
@@ -57,6 +57,7 @@
#if !defined(_LOCORE)
+#if 1
/*
* cache_r4k_op_line:
*
@@ -306,49 +307,15 @@ cache_r4k_op_8lines_NN_4way(size_t n, re
cache_r4k_op_8lines_NN_4way(64, (va1), (va2), (va3), (va4), (op))
#define cache_r4k_op_8lines_128_4way(va1, va2, va3, va4, op) \
cache_r4k_op_8lines_NN_4way(128, (va1), (va2), (va3), (va4), (op))
+#endif
-void r4k_icache_sync_all_16(void);
-void r4k_icache_sync_range_16(register_t, vsize_t);
-void r4k_icache_sync_range_index_16(vaddr_t, vsize_t);
-
-void r4k_icache_sync_all_32(void);
-void r4k_icache_sync_range_32(register_t, vsize_t);
-void r4k_icache_sync_range_index_32(vaddr_t, vsize_t);
-
-void r4k_pdcache_wbinv_all_16(void);
-void r4k_pdcache_wbinv_range_16(register_t, vsize_t);
-void r4k_pdcache_wbinv_range_index_16(vaddr_t, vsize_t);
-
-void r4k_pdcache_inv_range_16(register_t, vsize_t);
-void r4k_pdcache_wb_range_16(register_t, vsize_t);
-
-void r4k_pdcache_wbinv_all_32(void);
-void r4k_pdcache_wbinv_range_32(register_t, vsize_t);
-void r4k_pdcache_wbinv_range_index_32(vaddr_t, vsize_t);
-
-void r4k_pdcache_inv_range_32(register_t, vsize_t);
-void r4k_pdcache_wb_range_32(register_t, vsize_t);
-
-void r4k_sdcache_wbinv_all_32(void);
-void r4k_sdcache_wbinv_range_32(register_t, vsize_t);
-void r4k_sdcache_wbinv_range_index_32(vaddr_t, vsize_t);
-
-void r4k_sdcache_inv_range_32(register_t, vsize_t);
-void r4k_sdcache_wb_range_32(register_t, vsize_t);
-
-void r4k_sdcache_wbinv_all_128(void);
-void r4k_sdcache_wbinv_range_128(register_t, vsize_t);
-void r4k_sdcache_wbinv_range_index_128(vaddr_t, vsize_t);
-
-void r4k_sdcache_inv_range_128(register_t, vsize_t);
-void r4k_sdcache_wb_range_128(register_t, vsize_t);
+/* cache_r4k.c */
+void r4k_icache_sync_all_generic(void);
+void r4k_icache_sync_range_generic(register_t, vsize_t);
+void r4k_icache_sync_range_index_generic(vaddr_t, vsize_t);
+void r4k_pdcache_wbinv_all_generic(void);
void r4k_sdcache_wbinv_all_generic(void);
-void r4k_sdcache_wbinv_range_generic(register_t, vsize_t);
-void r4k_sdcache_wbinv_range_index_generic(vaddr_t, vsize_t);
-
-void r4k_sdcache_inv_range_generic(register_t, vsize_t);
-void r4k_sdcache_wb_range_generic(register_t, vsize_t);
/* cache_r4k_pcache16.S */
@@ -359,6 +326,13 @@ void cache_r4k_pdcache_hit_inv_16(regist
void cache_r4k_pdcache_hit_wb_inv_16(register_t, vsize_t);
void cache_r4k_pdcache_hit_wb_16(register_t, vsize_t);
+/* cache_r4k_scache16.S */
+
+void cache_r4k_sdcache_index_wb_inv_16(vaddr_t, vsize_t);
+void cache_r4k_sdcache_hit_inv_16(register_t, vsize_t);
+void cache_r4k_sdcache_hit_wb_inv_16(register_t, vsize_t);
+void cache_r4k_sdcache_hit_wb_16(register_t, vsize_t);
+
/* cache_r4k_pcache32.S */
void cache_r4k_icache_index_inv_32(vaddr_t, vsize_t);
@@ -368,6 +342,13 @@ void cache_r4k_pdcache_hit_inv_32(regist
void cache_r4k_pdcache_hit_wb_inv_32(register_t, vsize_t);
void cache_r4k_pdcache_hit_wb_32(register_t, vsize_t);
+/* cache_r4k_scache32.S */
+
+void cache_r4k_sdcache_index_wb_inv_32(vaddr_t, vsize_t);
+void cache_r4k_sdcache_hit_inv_32(register_t, vsize_t);
+void cache_r4k_sdcache_hit_wb_inv_32(register_t, vsize_t);
+void cache_r4k_sdcache_hit_wb_32(register_t, vsize_t);
+
/* cache_r4k_pcache64.S */
void cache_r4k_icache_index_inv_64(vaddr_t, vsize_t);
@@ -377,6 +358,13 @@ void cache_r4k_pdcache_hit_inv_64(regist
void cache_r4k_pdcache_hit_wb_inv_64(register_t, vsize_t);
void cache_r4k_pdcache_hit_wb_64(register_t, vsize_t);
+/* cache_r4k_scache64.S */
+
+void cache_r4k_sdcache_index_wb_inv_64(vaddr_t, vsize_t);
+void cache_r4k_sdcache_hit_inv_64(register_t, vsize_t);
+void cache_r4k_sdcache_hit_wb_inv_64(register_t, vsize_t);
+void cache_r4k_sdcache_hit_wb_64(register_t, vsize_t);
+
/* cache_r4k_pcache128.S */
void cache_r4k_icache_index_inv_128(vaddr_t, vsize_t);
@@ -385,6 +373,9 @@ void cache_r4k_pdcache_index_wb_inv_128(
void cache_r4k_pdcache_hit_inv_128(register_t, vsize_t);
void cache_r4k_pdcache_hit_wb_inv_128(register_t, vsize_t);
void cache_r4k_pdcache_hit_wb_128(register_t, vsize_t);
+
+/* cache_r4k_scache128.S */
+
void cache_r4k_sdcache_index_wb_inv_128(vaddr_t, vsize_t);
void cache_r4k_sdcache_hit_inv_128(register_t, vsize_t);
void cache_r4k_sdcache_hit_wb_inv_128(register_t, vsize_t);
Index: src/sys/arch/mips/mips/cache.c
diff -u src/sys/arch/mips/mips/cache.c:1.51 src/sys/arch/mips/mips/cache.c:1.52
--- src/sys/arch/mips/mips/cache.c:1.51 Mon Jul 11 16:15:36 2016
+++ src/sys/arch/mips/mips/cache.c Mon Jul 11 23:06:54 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.c,v 1.51 2016/07/11 16:15:36 matt Exp $ */
+/* $NetBSD: cache.c,v 1.52 2016/07/11 23:06:54 matt Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.51 2016/07/11 16:15:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.52 2016/07/11 23:06:54 matt Exp $");
#include "opt_cputype.h"
#include "opt_mips_cache.h"
@@ -416,23 +416,20 @@ mips_config_cache_prehistoric(void)
if (mci->mci_pdcache_size > PAGE_SIZE)
mci->mci_cache_virtual_alias = true;
+ mco->mco_icache_sync_all = r4k_icache_sync_all_generic;
switch (mci->mci_picache_line_size) {
case 16:
- mco->mco_icache_sync_all =
- r4k_icache_sync_all_16;
mco->mco_icache_sync_range =
- r4k_icache_sync_range_16;
+ cache_r4k_icache_hit_inv_16;
mco->mco_icache_sync_range_index =
- r4k_icache_sync_range_index_16;
+ cache_r4k_icache_index_inv_16;
break;
case 32:
- mco->mco_icache_sync_all =
- r4k_icache_sync_all_32;
mco->mco_icache_sync_range =
- r4k_icache_sync_range_32;
+ cache_r4k_icache_hit_inv_32;
mco->mco_icache_sync_range_index =
- r4k_icache_sync_range_index_32;
+ cache_r4k_icache_index_inv_32;
break;
default:
@@ -440,31 +437,28 @@ mips_config_cache_prehistoric(void)
mci->mci_picache_line_size);
}
+ mco->mco_pdcache_wbinv_all = r4k_pdcache_wbinv_all_generic;
switch (mci->mci_pdcache_line_size) {
case 16:
- mco->mco_pdcache_wbinv_all =
- r4k_pdcache_wbinv_all_16;
mco->mco_pdcache_wbinv_range =
- r4k_pdcache_wbinv_range_16;
+ cache_r4k_pdcache_hit_wb_inv_16;
mco->mco_pdcache_wbinv_range_index =
- r4k_pdcache_wbinv_range_index_16;
+ cache_r4k_pdcache_index_wb_inv_16;
mco->mco_pdcache_inv_range =
- r4k_pdcache_inv_range_16;
+ cache_r4k_pdcache_hit_inv_16;
mco->mco_pdcache_wb_range =
- r4k_pdcache_wb_range_16;
+ cache_r4k_pdcache_hit_wb_16;
break;
case 32:
- mco->mco_pdcache_wbinv_all =
- r4k_pdcache_wbinv_all_32;
mco->mco_pdcache_wbinv_range =
- r4k_pdcache_wbinv_range_32;
+ cache_r4k_pdcache_hit_wb_inv_32;
mco->mco_pdcache_wbinv_range_index =
- r4k_pdcache_wbinv_range_index_32;
+ cache_r4k_pdcache_index_wb_inv_32;
mco->mco_pdcache_inv_range =
- r4k_pdcache_inv_range_32;
+ cache_r4k_pdcache_hit_inv_32;
mco->mco_pdcache_wb_range =
- r4k_pdcache_wb_range_32;
+ cache_r4k_pdcache_hit_wb_32;
break;
default:
@@ -730,45 +724,51 @@ primary_cache_is_2way:
#endif
switch (mci->mci_sdcache_ways) {
case 1:
+ mco->mco_sdcache_wbinv_all =
+ r4k_sdcache_wbinv_all_generic;
switch (mci->mci_sdcache_line_size) {
+ case 16:
+ mco->mco_sdcache_wbinv_range =
+ cache_r4k_sdcache_hit_wb_inv_16;
+ mco->mco_sdcache_wbinv_range_index =
+ cache_r4k_sdcache_index_wb_inv_16;
+ mco->mco_sdcache_inv_range =
+ cache_r4k_sdcache_hit_inv_16;
+ mco->mco_sdcache_wb_range =
+ cache_r4k_sdcache_hit_wb_16;
+ break;
+
case 32:
- mco->mco_sdcache_wbinv_all =
- r4k_sdcache_wbinv_all_32;
mco->mco_sdcache_wbinv_range =
- r4k_sdcache_wbinv_range_32;
+ cache_r4k_sdcache_hit_wb_inv_32;
mco->mco_sdcache_wbinv_range_index =
- r4k_sdcache_wbinv_range_index_32;
+ cache_r4k_sdcache_index_wb_inv_32;
mco->mco_sdcache_inv_range =
- r4k_sdcache_inv_range_32;
+ cache_r4k_sdcache_hit_inv_32;
mco->mco_sdcache_wb_range =
- r4k_sdcache_wb_range_32;
+ cache_r4k_sdcache_hit_wb_32;
break;
- case 16:
case 64:
- mco->mco_sdcache_wbinv_all =
- r4k_sdcache_wbinv_all_generic;
mco->mco_sdcache_wbinv_range =
- r4k_sdcache_wbinv_range_generic;
+ cache_r4k_sdcache_hit_wb_inv_64;
mco->mco_sdcache_wbinv_range_index =
- r4k_sdcache_wbinv_range_index_generic;
+ cache_r4k_sdcache_index_wb_inv_64;
mco->mco_sdcache_inv_range =
- r4k_sdcache_inv_range_generic;
+ cache_r4k_sdcache_hit_inv_64;
mco->mco_sdcache_wb_range =
- r4k_sdcache_wb_range_generic;
+ cache_r4k_sdcache_hit_wb_64;
break;
case 128:
- mco->mco_sdcache_wbinv_all =
- r4k_sdcache_wbinv_all_128;
mco->mco_sdcache_wbinv_range =
- r4k_sdcache_wbinv_range_128;
+ cache_r4k_sdcache_hit_wb_inv_128;
mco->mco_sdcache_wbinv_range_index =
- r4k_sdcache_wbinv_range_index_128;
+ cache_r4k_sdcache_index_wb_inv_128;
mco->mco_sdcache_inv_range =
- r4k_sdcache_inv_range_128;
+ cache_r4k_sdcache_hit_inv_128;
mco->mco_sdcache_wb_range =
- r4k_sdcache_wb_range_128;
+ cache_r4k_sdcache_hit_wb_128;
break;
default:
Index: src/sys/arch/mips/mips/cache_r4k.c
diff -u src/sys/arch/mips/mips/cache_r4k.c:1.13 src/sys/arch/mips/mips/cache_r4k.c:1.14
--- src/sys/arch/mips/mips/cache_r4k.c:1.13 Mon Jul 11 16:15:36 2016
+++ src/sys/arch/mips/mips/cache_r4k.c Mon Jul 11 23:06:54 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_r4k.c,v 1.13 2016/07/11 16:15:36 matt Exp $ */
+/* $NetBSD: cache_r4k.c,v 1.14 2016/07/11 23:06:54 matt Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache_r4k.c,v 1.13 2016/07/11 16:15:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache_r4k.c,v 1.14 2016/07/11 23:06:54 matt Exp $");
#include <sys/param.h>
@@ -54,236 +54,27 @@ __KERNEL_RCSID(0, "$NetBSD: cache_r4k.c,
* XXX Does not handle split secondary caches.
*/
-#define round_line(x) (((x) + 15) & ~15)
-#define trunc_line(x) ((x) & ~15)
-
-__asm(".set mips3");
-
-void
-r4k_icache_sync_all_16(void)
-{
- vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
- vaddr_t eva = va + mips_cache_info.mci_picache_size;
-
- mips_dcache_wbinv_all();
-
- __asm volatile("sync");
-
- while (va < eva) {
- cache_r4k_op_32lines_16(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
- va += (32 * 16);
- }
-}
-
-void
-r4k_icache_sync_range_16(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- mips_dcache_wb_range(va, (eva - va));
-
- __asm volatile("sync");
-
- while ((eva - va) >= (32 * 16)) {
- cache_r4k_op_32lines_16(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
- va += (32 * 16);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
- va += 16;
- }
-}
-
-void
-r4k_icache_sync_range_index_16(vaddr_t va, vsize_t size)
-{
- vaddr_t eva, orig_va;
-
- orig_va = va;
-
- eva = round_line(va + size);
- va = trunc_line(va);
-
- mips_dcache_wbinv_range_index(va, (eva - va));
-
- __asm volatile("sync");
-
- /*
- * Since we're doing Index ops, we expect to not be able
- * to access the address we've been given. So, get the
- * bits that determine the cache index, and make a KSEG0
- * address out of them.
- */
- va = MIPS_PHYS_TO_KSEG0(orig_va & mips_cache_info.mci_picache_way_mask);
-
- eva = round_line(va + size);
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 16)) {
- cache_r4k_op_32lines_16(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
- va += (32 * 16);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
- va += 16;
- }
-}
-
-void
-r4k_pdcache_wbinv_all_16(void)
-{
- vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
- vaddr_t eva = va + mips_cache_info.mci_pdcache_size;
-
- while (va < eva) {
- cache_r4k_op_32lines_16(va,
- CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
- va += (32 * 16);
- }
-}
-
-void
-r4k_pdcache_wbinv_range_16(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 16)) {
- cache_r4k_op_32lines_16(va,
- CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
- va += (32 * 16);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
- va += 16;
- }
-}
-
-void
-r4k_pdcache_wbinv_range_index_16(vaddr_t va, vsize_t size)
-{
- vaddr_t eva;
-
- /*
- * Since we're doing Index ops, we expect to not be able
- * to access the address we've been given. So, get the
- * bits that determine the cache index, and make a KSEG0
- * address out of them.
- */
- va = MIPS_PHYS_TO_KSEG0(va & (mips_cache_info.mci_pdcache_size - 1));
-
- eva = round_line(va + size);
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 16)) {
- cache_r4k_op_32lines_16(va,
- CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
- va += (32 * 16);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
- va += 16;
- }
-}
-
-void
-r4k_pdcache_inv_range_16(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 16)) {
- cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
- va += (32 * 16);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
- va += 16;
- }
-}
-
-void
-r4k_pdcache_wb_range_16(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 16)) {
- cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
- va += (32 * 16);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
- va += 16;
- }
-}
-
-#undef round_line
-#undef trunc_line
-
-#define round_line(x) (((x) + 31) & ~31)
-#define trunc_line(x) ((x) & ~31)
-
void
-r4k_icache_sync_all_32(void)
+r4k_icache_sync_all_generic(void)
{
- vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
- vaddr_t eva = va + mips_cache_info.mci_picache_size;
-
mips_dcache_wbinv_all();
- __asm volatile("sync");
-
- while (va < eva) {
- cache_r4k_op_32lines_32(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
- va += (32 * 32);
- }
+ mips_intern_icache_sync_range_index(MIPS_PHYS_TO_KSEG0(0),
+ mips_cache_info.mci_picache_size);
}
void
-r4k_icache_sync_range_32(register_t va, vsize_t size)
+r4k_icache_sync_range_generic(register_t va, vsize_t size)
{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
+ mips_dcache_wb_range(va, size);
- mips_dcache_wb_range(va, (eva - va));
-
- __asm volatile("sync");
-
- while ((eva - va) >= (32 * 32)) {
- cache_r4k_op_32lines_32(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
- va += (32 * 32);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
- va += 32;
- }
+ mips_intern_icache_sync_range_index(va, size);
}
void
-r4k_icache_sync_range_index_32(vaddr_t va, vsize_t size)
+r4k_icache_sync_range_index_generic(vaddr_t va, vsize_t size)
{
- vaddr_t eva;
-
- eva = round_line(va + size);
- va = trunc_line(va);
-
- mips_dcache_wbinv_range_index(va, (eva - va));
-
- __asm volatile("sync");
+ mips_dcache_wbinv_range_index(va, size);
/*
* Since we're doing Index ops, we expect to not be able
@@ -292,398 +83,21 @@ r4k_icache_sync_range_index_32(vaddr_t v
* address out of them.
*/
va = MIPS_PHYS_TO_KSEG0(va & mips_cache_info.mci_picache_way_mask);
+ size &= mips_cache_info.mci_picache_way_mask;
- eva = round_line(va + size);
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 32)) {
- cache_r4k_op_32lines_32(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
- va += (32 * 32);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
- va += 32;
- }
-}
-
-void
-r4k_pdcache_wbinv_all_32(void)
-{
- vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
- vaddr_t eva = va + mips_cache_info.mci_pdcache_size;
-
- while (va < eva) {
- cache_r4k_op_32lines_32(va,
- CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
- va += (32 * 32);
- }
-}
-
-void
-r4k_pdcache_wbinv_range_32(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 32)) {
- cache_r4k_op_32lines_32(va,
- CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
- va += (32 * 32);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
- va += 32;
- }
-}
-
-void
-r4k_pdcache_wbinv_range_index_32(vaddr_t va, vsize_t size)
-{
- vaddr_t eva;
-
- /*
- * Since we're doing Index ops, we expect to not be able
- * to access the address we've been given. So, get the
- * bits that determine the cache index, and make a KSEG0
- * address out of them.
- */
- va = MIPS_PHYS_TO_KSEG0(va & (mips_cache_info.mci_pdcache_size - 1));
-
- eva = round_line(va + size);
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 32)) {
- cache_r4k_op_32lines_32(va,
- CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
- va += (32 * 32);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
- va += 32;
- }
-}
-
-void
-r4k_pdcache_inv_range_32(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 32)) {
- cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
- va += (32 * 32);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
- va += 32;
- }
-}
-
-void
-r4k_pdcache_wb_range_32(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 32)) {
- cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
- va += (32 * 32);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
- va += 32;
- }
-}
-
-void
-r4k_sdcache_wbinv_all_32(void)
-{
- vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
- vaddr_t eva = va + mips_cache_info.mci_sdcache_size;
-
- while (va < eva) {
- cache_r4k_op_32lines_32(va,
- CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
- va += (32 * 32);
- }
-}
-
-void
-r4k_sdcache_wbinv_range_32(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 32)) {
- cache_r4k_op_32lines_32(va,
- CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV);
- va += (32 * 32);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV);
- va += 32;
- }
-}
-
-void
-r4k_sdcache_wbinv_range_index_32(vaddr_t va, vsize_t size)
-{
- vaddr_t eva;
-
- /*
- * Since we're doing Index ops, we expect to not be able
- * to access the address we've been given. So, get the
- * bits that determine the cache index, and make a KSEG0
- * address out of them.
- */
- va = MIPS_PHYS_TO_KSEG0(va & (mips_cache_info.mci_sdcache_size - 1));
-
- eva = round_line(va + size);
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 32)) {
- cache_r4k_op_32lines_32(va,
- CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
- va += (32 * 32);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
- va += 32;
- }
-}
-
-void
-r4k_sdcache_inv_range_32(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 32)) {
- cache_r4k_op_32lines_32(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV);
- va += (32 * 32);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV);
- va += 32;
- }
-}
-
-void
-r4k_sdcache_wb_range_32(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 32)) {
- cache_r4k_op_32lines_32(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB);
- va += (32 * 32);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB);
- va += 32;
- }
-}
-
-#undef round_line
-#undef trunc_line
-
-#define round_line(x) (((x) + 127) & ~127)
-#define trunc_line(x) ((x) & ~127)
-
-void
-r4k_sdcache_wbinv_all_128(void)
-{
- vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
- vaddr_t eva = va + mips_cache_info.mci_sdcache_size;
-
- while (va < eva) {
- cache_r4k_op_32lines_128(va,
- CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
- va += (32 * 128);
- }
-}
-
-void
-r4k_sdcache_wbinv_range_128(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 128)) {
- cache_r4k_op_32lines_128(va,
- CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV);
- va += (32 * 128);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV);
- va += 128;
- }
-}
-
-void
-r4k_sdcache_wbinv_range_index_128(vaddr_t va, vsize_t size)
-{
- vaddr_t eva;
-
- /*
- * Since we're doing Index ops, we expect to not be able
- * to access the address we've been given. So, get the
- * bits that determine the cache index, and make a KSEG0
- * address out of them.
- */
- va = MIPS_PHYS_TO_KSEG0(va & (mips_cache_info.mci_sdcache_size - 1));
-
- eva = round_line(va + size);
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 128)) {
- cache_r4k_op_32lines_128(va,
- CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
- va += (32 * 128);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
- va += 128;
- }
+ mips_intern_icache_sync_range_index(va, size);
}
void
-r4k_sdcache_inv_range_128(register_t va, vsize_t size)
+r4k_pdcache_wbinv_all_generic(void)
{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 128)) {
- cache_r4k_op_32lines_128(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV);
- va += (32 * 128);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV);
- va += 128;
- }
-}
-
-void
-r4k_sdcache_wb_range_128(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
-
- va = trunc_line(va);
-
- while ((eva - va) >= (32 * 128)) {
- cache_r4k_op_32lines_128(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB);
- va += (32 * 128);
- }
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB);
- va += 128;
- }
+ mips_intern_pdcache_wbinv_range_index(MIPS_PHYS_TO_KSEG0(0),
+ mips_cache_info.mci_pdcache_size);
}
-#undef round_line
-#undef trunc_line
-
-#define round_line(x) (((x) + mips_cache_info.mci_sdcache_line_size - 1) & ~(mips_cache_info.mci_sdcache_line_size - 1))
-#define trunc_line(x) ((x) & ~(mips_cache_info.mci_sdcache_line_size - 1))
-
void
r4k_sdcache_wbinv_all_generic(void)
{
- vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
- vaddr_t eva = va + mips_cache_info.mci_sdcache_size;
- int line_size = mips_cache_info.mci_sdcache_line_size;
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
- va += line_size;
- }
-}
-
-void
-r4k_sdcache_wbinv_range_generic(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
- int line_size = mips_cache_info.mci_sdcache_line_size;
-
- va = trunc_line(va);
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV);
- va += line_size;
- }
-}
-
-void
-r4k_sdcache_wbinv_range_index_generic(vaddr_t va, vsize_t size)
-{
- vaddr_t eva;
- int line_size = mips_cache_info.mci_sdcache_line_size;
-
- /*
- * Since we're doing Index ops, we expect to not be able
- * to access the address we've been given. So, get the
- * bits that determine the cache index, and make a KSEG0
- * address out of them.
- */
- va = MIPS_PHYS_TO_KSEG0(va & (mips_cache_info.mci_sdcache_size - 1));
-
- eva = round_line(va + size);
- va = trunc_line(va);
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
- va += line_size;
- }
-}
-
-void
-r4k_sdcache_inv_range_generic(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
- int line_size = mips_cache_info.mci_sdcache_line_size;
-
- va = trunc_line(va);
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV);
- va += line_size;
- }
+ mips_intern_sdcache_wbinv_range_index(MIPS_PHYS_TO_KSEG0(0),
+ mips_cache_info.mci_sdcache_size);
}
-
-void
-r4k_sdcache_wb_range_generic(register_t va, vsize_t size)
-{
- vaddr_t eva = round_line(va + size);
- int line_size = mips_cache_info.mci_sdcache_line_size;
-
- va = trunc_line(va);
-
- while (va < eva) {
- cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB);
- va += line_size;
- }
-}
-
-#undef round_line
-#undef trunc_line
