Module Name: src
Committed By: jakllsch
Date: Mon Sep 26 20:08:58 UTC 2016
Modified Files:
src/sys/arch/arm/nvidia: tegra_xusbpadreg.h
Log Message:
Add register definitions that will be necessary for future
tegraxusbpadctl(4) changes.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/nvidia/tegra_xusbpadreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/nvidia/tegra_xusbpadreg.h
diff -u src/sys/arch/arm/nvidia/tegra_xusbpadreg.h:1.1 src/sys/arch/arm/nvidia/tegra_xusbpadreg.h:1.2
--- src/sys/arch/arm/nvidia/tegra_xusbpadreg.h:1.1 Fri May 15 11:49:10 2015
+++ src/sys/arch/arm/nvidia/tegra_xusbpadreg.h Mon Sep 26 20:08:58 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_xusbpadreg.h,v 1.1 2015/05/15 11:49:10 jmcneill Exp $ */
+/* $NetBSD: tegra_xusbpadreg.h,v 1.2 2016/09/26 20:08:58 jakllsch Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -118,6 +118,31 @@
#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5_REG 0x158
#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6_REG 0x15c
+#define XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_VCORE_DOWN __BIT(18)
+#define XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN_EARLY __BIT(17)
+#define XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN __BIT(16)
+
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI __BIT(21)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 __BIT(20)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD __BIT(19)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW __BITS(15,14)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(pad) ((pad >= 1) ? 0x0 : 0x3)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW __BITS(11,6)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL 0x0e
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL __BITS(5,0)
+
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP __BITS(10,9)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ __BITS(6,3)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR __BIT(2)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP __BIT(1)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP __BIT(0)
+
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD_TRK __BIT(13)
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD __BIT(12)
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL __BITS(4,2)
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x5
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL __BITS(1,0)
+
#define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0 __BITS(27,26)
#define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_PCIE 0
#define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_USB3_SS 1
