Module Name: src
Committed By: maya
Date: Fri Nov 11 16:49:30 UTC 2016
Modified Files:
src/sys/arch/mips/mips: spl.S
Log Message:
switch post-mfc0 call "hazard barrier" from NOP_L to MFC0_HAZARD.
this means it will be applied if MIPS3 too, and now with the prior
commit, it will be a superscalar nop, not just a plain nop.
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/mips/mips/spl.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/spl.S
diff -u src/sys/arch/mips/mips/spl.S:1.13 src/sys/arch/mips/mips/spl.S:1.14
--- src/sys/arch/mips/mips/spl.S:1.13 Fri Nov 11 16:45:14 2016
+++ src/sys/arch/mips/mips/spl.S Fri Nov 11 16:49:30 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: spl.S,v 1.13 2016/11/11 16:45:14 maya Exp $ */
+/* $NetBSD: spl.S,v 1.14 2016/11/11 16:49:30 maya Exp $ */
/*-
* Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include <mips/asm.h>
#include <mips/cpuregs.h>
-RCSID("$NetBSD: spl.S,v 1.13 2016/11/11 16:45:14 maya Exp $")
+RCSID("$NetBSD: spl.S,v 1.14 2016/11/11 16:49:30 maya Exp $")
#include "assym.h"
@@ -76,7 +76,7 @@ _splraise:
bnez v1, 1f # yes, don't change.
nop # branch delay
mfc0 v1, MIPS_COP_0_STATUS # fetch status register
- NOP_L # load delay
+ MFC0_HAZARD # load delay
or v1, MIPS_INT_MASK # enable all interrupts
xor a0, v1 # disable ipl's masked bits
DYNAMIC_STATUS_MASK(a0,v0) # machine dependent masking
@@ -101,7 +101,7 @@ _splraise:
1:
#ifdef PARANOIA
mfc0 v1, MIPS_COP_0_STATUS
- NOP_L # load delay
+ MFC0_HAZARD # load delay
and a0, v1 # a1 contains bit that MBZ
3: bnez a0, 3b # loop forever
nop # branch delay
@@ -167,7 +167,7 @@ STATIC_LEAF(_splsw_spl0)
or v1, MIPS_SR_INT_IE # mask sure interrupts are on
xor v1, MIPS_INT_MASK # invert
mfc0 a0, MIPS_COP_0_STATUS
- NOP_L # load delay
+ MFC0_HAZARD # load delay
or v0, a0, v1
DYNAMIC_STATUS_MASK(v0,t0) # machine dependent masking
mtc0 zero, MIPS_COP_0_STATUS ## disable interrupts
@@ -186,7 +186,7 @@ STATIC_LEAF(_splsw_setsoftintr)
mtc0 zero, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
COP0_SYNC
mfc0 v0, MIPS_COP_0_CAUSE # fetch cause register
- NOP_L # load delay
+ MFC0_HAZARD # load delay
or v0, v0, a0 # set soft intr. bits
mtc0 v0, MIPS_COP_0_CAUSE # store back
COP0_SYNC
@@ -228,7 +228,7 @@ STATIC_XLEAF(_splsw_splhigh_noprof)
beq v0, a1, 1f # don't do anything if IPL_HIGH
nop # branch delay
mfc0 v1, MIPS_COP_0_STATUS # fetch status register
- NOP_L # load delay
+ MFC0_HAZARD # load delay
and a0, v1, MIPS_INT_MASK # select all interrupts
xor a0, v1 # clear all interrupts
DYNAMIC_STATUS_MASK(a0,a2) # machine dependent masking
@@ -306,7 +306,7 @@ END(_splsw_splsoftclock)
STATIC_LEAF(_splsw_splintr)
mfc0 ta1, MIPS_COP_0_CAUSE # get active interrupts
- NOP_L # load delay
+ MFC0_HAZARD # load delay
# restrict to hard int bits
and v1, ta1, MIPS_HARD_INT_MASK # now have pending interrupts
li v0, IPL_NONE # return IPL_NONE
