Module Name: src
Committed By: maya
Date: Mon Jan 16 10:15:42 UTC 2017
Modified Files:
src/sys/arch/aarch64/include: pte.h
Log Message:
Correct definitions for TCR.
Values from ARM Cortex A-53 MPCore Processor Technical Reference Manual
4.3.48. Translation Control Register, EL1
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/aarch64/include/pte.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/include/pte.h
diff -u src/sys/arch/aarch64/include/pte.h:1.1 src/sys/arch/aarch64/include/pte.h:1.2
--- src/sys/arch/aarch64/include/pte.h:1.1 Sun Aug 10 05:47:38 2014
+++ src/sys/arch/aarch64/include/pte.h Mon Jan 16 10:15:42 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.1 2014/08/10 05:47:38 matt Exp $ */
+/* $NetBSD: pte.h,v 1.2 2017/01/16 10:15:42 maya Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -107,8 +107,8 @@ typedef unsigned long long pt_entry_t;
#define TCR_T1SZ __BITS(21,16) // Size offset for TTBR1_EL1
#define TCR_TG0 __BITS(15,14)
#define TCR_SH0 __BITS(13,12)
-#define TCR_ORGN1 __BITS(11,10)
-#define TCR_IRGN1 __BITS(9,8)
+#define TCR_ORGN0 __BITS(11,10)
+#define TCR_IRGN0 __BITS(9,8)
#define TCR_EPD0 __BIT(7) // Walk Disable for TTBR0
#define TCR_T0SZ __BITS(5,0) // Size offset for TTBR0_EL1
