Module Name: src
Committed By: jakllsch
Date: Sun Jan 22 17:43:23 UTC 2017
Modified Files:
src/sys/arch/arm/nvidia: tegra_mcreg.h
Log Message:
Add some SMMU registers and bit definitions.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/nvidia/tegra_mcreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/nvidia/tegra_mcreg.h
diff -u src/sys/arch/arm/nvidia/tegra_mcreg.h:1.2 src/sys/arch/arm/nvidia/tegra_mcreg.h:1.3
--- src/sys/arch/arm/nvidia/tegra_mcreg.h:1.2 Sat Nov 21 16:48:33 2015
+++ src/sys/arch/arm/nvidia/tegra_mcreg.h Sun Jan 22 17:43:23 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_mcreg.h,v 1.2 2015/11/21 16:48:33 jakllsch Exp $ */
+/* $NetBSD: tegra_mcreg.h,v 1.3 2017/01/22 17:43:23 jakllsch Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -78,4 +78,12 @@
#define MC_EMEM_CFG_0_EMEM_BOM __BIT(31)
#define MC_EMEM_CFG_0_EMEM_SIZE_MB __BITS(13,0)
+#define MC_SMMU_TRANSLATION_ENABLE_0_REG 0x228
+#define MC_SMMU_AFIR_ENABLE __BIT(14)
+#define MC_SMMU_TRANSLATION_ENABLE_1_REG 0x22c
+#define MC_SMMU_AFIW_ENABLE __BIT(17)
+#define MC_SMMU_TRANSLATION_ENABLE_2_REG 0x230
+#define MC_SMMU_TRANSLATION_ENABLE_3_REG 0x234
+#define MC_SMMU_AFI_ASID_REG 0x238
+
#endif /* _ARM_TEGRA_MCREG_H */
