Module Name: src
Committed By: maxv
Date: Sat Mar 11 10:33:46 UTC 2017
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: pmc.c
src/usr.bin/pmc: pmc.c
Log Message:
Add the AMD 10h family, with additional events that I believe are useful,
the DTLB misses on large pages for example.
While here, remove a few K7 flags that do not actually exist on K7 (there
must have been a confusion between K7 and K8); and make the 'pmc list'
command a little more user-friendly.
To generate a diff of this commit:
cvs rdiff -u -r1.94 -r1.95 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/x86/x86/pmc.c
cvs rdiff -u -r1.21 -r1.22 src/usr.bin/pmc/pmc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.94 src/sys/arch/x86/include/specialreg.h:1.95
--- src/sys/arch/x86/include/specialreg.h:1.94 Sat Feb 18 16:15:51 2017
+++ src/sys/arch/x86/include/specialreg.h Sat Mar 11 10:33:46 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.94 2017/02/18 16:15:51 maxv Exp $ */
+/* $NetBSD: specialreg.h,v 1.95 2017/03/11 10:33:46 maxv Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -997,94 +997,51 @@
#define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */
/*
- * AMD K7 Event Selector MSR format. [Doc: 22007K.pdf, Feb 2002]
+ * AMD K7. [Doc: 22007K.pdf, Feb 2002]
*/
-
+/* Event Selector MSR format */
#define K7_EVTSEL_EVENT 0x000000ff
#define K7_EVTSEL_UNIT 0x0000ff00
#define K7_EVTSEL_UNIT_SHIFT 8
-#define K7_EVTSEL_USR (1 << 16)
-#define K7_EVTSEL_OS (1 << 17)
-#define K7_EVTSEL_E (1 << 18)
-#define K7_EVTSEL_PC (1 << 19)
-#define K7_EVTSEL_INT (1 << 20)
-#define K7_EVTSEL_EN (1 << 22)
-#define K7_EVTSEL_INV (1 << 23)
+#define K7_EVTSEL_USR __BIT(16)
+#define K7_EVTSEL_OS __BIT(17)
+#define K7_EVTSEL_E __BIT(18)
+#define K7_EVTSEL_PC __BIT(19)
+#define K7_EVTSEL_INT __BIT(20)
+#define K7_EVTSEL_EN __BIT(22)
+#define K7_EVTSEL_INV __BIT(23)
#define K7_EVTSEL_COUNTER_MASK 0xff000000
#define K7_EVTSEL_COUNTER_MASK_SHIFT 24
-
-/* Segment Register Loads */
-#define K7_SEGMENT_REG_LOADS 0x20
-
-#define K7_STORES_TO_ACTIVE_INST_STREAM 0x21
-
/* Data Cache Unit */
#define K7_DATA_CACHE_ACCESS 0x40
#define K7_DATA_CACHE_MISS 0x41
#define K7_DATA_CACHE_REFILL 0x42
#define K7_DATA_CACHE_REFILL_SYSTEM 0x43
#define K7_DATA_CACHE_WBACK 0x44
-#define K7_L2_DTLB_HIT 0x45
+#define K7_L1_DTLB_MISS 0x45
#define K7_L2_DTLB_MISS 0x46
#define K7_MISALIGNED_DATA_REF 0x47
-#define K7_SYSTEM_REQUEST 0x64
-#define K7_SYSTEM_REQUEST_TYPE 0x65
-
-#define K7_SNOOP_HIT 0x73
-#define K7_SINGLE_BIT_ECC_ERROR 0x74
-#define K7_CACHE_LINE_INVAL 0x75
-#define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76
-#define K7_L2_REQUEST 0x79
-#define K7_L2_REQUEST_BUSY 0x7a
-
/* Instruction Fetch Unit */
#define K7_IFU_IFETCH 0x80
#define K7_IFU_IFETCH_MISS 0x81
#define K7_IFU_REFILL_FROM_L2 0x82
#define K7_IFU_REFILL_FROM_SYSTEM 0x83
-#define K7_ITLB_L1_MISS 0x84
-#define K7_ITLB_L2_MISS 0x85
-#define K7_SNOOP_RESYNC 0x86
-#define K7_IFU_STALL 0x87
-
-#define K7_RETURN_STACK_HITS 0x88
-#define K7_RETURN_STACK_OVERFLOW 0x89
-
+#define K7_L1_ITLB_MISS 0x84
+#define K7_L2_ITLB_MISS 0x85
/* Retired */
#define K7_RETIRED_INST 0xc0
#define K7_RETIRED_OPS 0xc1
-#define K7_RETIRED_BRANCHES 0xc2
+#define K7_RETIRED_BRANCH 0xc2
#define K7_RETIRED_BRANCH_MISPREDICTED 0xc3
#define K7_RETIRED_TAKEN_BRANCH 0xc4
#define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5
#define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6
#define K7_RETIRED_RESYNC_BRANCH 0xc7
-#define K7_RETIRED_NEAR_RETURNS 0xc8
-#define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9
-#define K7_RETIRED_INDIRECT_MISPREDICTED 0xca
-
/* Interrupts */
#define K7_CYCLES_INT_MASKED 0xcd
#define K7_CYCLES_INT_PENDING_AND_MASKED 0xce
#define K7_HW_INTR_RECV 0xcf
-#define K7_INSTRUCTION_DECODER_EMPTY 0xd0
-#define K7_DISPATCH_STALLS 0xd1
-#define K7_BRANCH_ABORTS_TO_RETIRE 0xd2
-#define K7_SERIALIZE 0xd3
-#define K7_SEGMENT_LOAD_STALL 0xd4
-#define K7_ICU_FULL 0xd5
-#define K7_RESERVATION_STATIONS_FULL 0xd6
-#define K7_FPU_FULL 0xd7
-#define K7_LS_FULL 0xd8
-#define K7_ALL_QUIET_STALL 0xd9
-#define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda
-
-#define K7_BP0_MATCH 0xdc
-#define K7_BP1_MATCH 0xdd
-#define K7_BP2_MATCH 0xde
-#define K7_BP3_MATCH 0xdf
-
/*
* AMD 10h family PMCs. [Doc: 31116.pdf, Jan 2013]
*/
@@ -1132,14 +1089,14 @@
#define F10H_CANCELLED_STORE_LOAD_FORWARD_OPS 0x2A
#define F10H_SMI_RECEIVED 0x2B
/* Data Cache Events */
-#define F10H_DATA_CACHE_ACCESSES 0x40
-#define F10H_DATA_CACHE_MISSES 0x41
-#define F10H_DATA_CACHE_REFILLS_FROM_L2 0x42
-#define F10H_DATA_CACHE_REFILLS_FROM_NORTHBRIDGE 0x43
+#define F10H_DATA_CACHE_ACCESS 0x40
+#define F10H_DATA_CACHE_MISS 0x41
+#define F10H_DATA_CACHE_REFILL_FROM_L2 0x42
+#define F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE 0x43
#define F10H_CACHE_LINES_EVICTED 0x44
#define F10H_L1_DTLB_MISS 0x45
#define F10H_L2_DTLB_MISS 0x46
-#define F10H_MISALIGNED_ACCESSES 0x47
+#define F10H_MISALIGNED_ACCESS 0x47
#define F10H_MICROARCH_LATE_CANCEL_OF_ACCESS 0x48
#define F10H_MICROARCH_EARLY_CANCEL_OF_ACCESS 0x49
#define F10H_SINGLE_BIT_ECC_ERRORS_RECORDED 0x4A
@@ -1160,10 +1117,10 @@
#define F10H_L2_FILL 0x7F
/* F10H_PAGE_SIZE_MISMATCHES (0x01C0): reserved on some revisions */
/* Instruction Cache Events */
-#define F10H_INSTRUCTION_CACHE_FETCHES 0x80
-#define F10H_INSTRUCTION_CACHE_MISSES 0x81
-#define F10H_INSTRUCTION_CACHE_REFILLS_FROM_L2 0x82
-#define F10H_INSTRUCTION_CACHE_REFILLS_FROM_SYS 0x83
+#define F10H_INSTRUCTION_CACHE_FETCH 0x80
+#define F10H_INSTRUCTION_CACHE_MISS 0x81
+#define F10H_INSTRUCTION_CACHE_REFILL_FROM_L2 0x82
+#define F10H_INSTRUCTION_CACHE_REFILL_FROM_SYS 0x83
#define F10H_L1_ITLB_MISS 0x84
#define F10H_L2_ITLB_MISS 0x85
#define F10H_PIPELINE_RESTART_INSTR_STREAM_PROBE 0x86
@@ -1177,15 +1134,15 @@
/* Execution Unit Events */
#define F10H_RETIRED_INSTRUCTIONS 0xC0
#define F10H_RETIRED_UOPS 0xC1
-#define F10H_RETIRED_BRANCH_INSTRUCTIONS 0xC2
-#define F10H_RETIRED_MISPREDICTED_BRANCH_INSTR 0xC3
-#define F10H_RETIRED_TAKEN_BRANCH_INSTRUCTIONS 0xC4
-#define F10H_RETIRED_TAKEN_BRANCH_INSTR_MISPREDICTED 0xC5
-#define F10H_RETIRED_FAR_CONTROL_TRANSFERS 0xC6
-#define F10H_RETIRED_BRANCH_RESYNCS 0xC7
+#define F10H_RETIRED_BRANCH 0xC2
+#define F10H_RETIRED_MISPREDICTED_BRANCH 0xC3
+#define F10H_RETIRED_TAKEN_BRANCH 0xC4
+#define F10H_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xC5
+#define F10H_RETIRED_FAR_CONTROL_TRANSFER 0xC6
+#define F10H_RETIRED_BRANCH_RESYNC 0xC7
#define F10H_RETIRED_NEAR_RETURNS 0xC8
#define F10H_RETIRED_NEAR_RETURNS_MISPREDICTED 0xC9
-#define F10H_RETIRED_INDIRECT_BRANCHES_MISPREDICTED 0xCA
+#define F10H_RETIRED_INDIRECT_BRANCH_MISPREDICTED 0xCA
#define F10H_RETIRED_MMX_FP_INSTRUCTIONS 0xCB
#define F10H_RETIRED_FASTPATH_DOUBLE_OP_INSTR 0xCC
#define F10H_INTERRUPTS_MASKED_CYCLES 0xCD
Index: src/sys/arch/x86/x86/pmc.c
diff -u src/sys/arch/x86/x86/pmc.c:1.1 src/sys/arch/x86/x86/pmc.c:1.2
--- src/sys/arch/x86/x86/pmc.c:1.1 Fri Mar 10 14:40:56 2017
+++ src/sys/arch/x86/x86/pmc.c Sat Mar 11 10:33:46 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: pmc.c,v 1.1 2017/03/10 14:40:56 maxv Exp $ */
+/* $NetBSD: pmc.c,v 1.2 2017/03/11 10:33:46 maxv Exp $ */
/*
* Copyright (c) 2017 The NetBSD Foundation, Inc.
@@ -67,7 +67,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmc.c,v 1.1 2017/03/10 14:40:56 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmc.c,v 1.2 2017/03/11 10:33:46 maxv Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -133,6 +133,7 @@ pmc_apply_cpu(void *arg1, void *arg2)
case PMC_TYPE_I686:
case PMC_TYPE_K7:
+ case PMC_TYPE_F10H:
wrmsr(pmc->evtmsr, pmc->evtval);
break;
}
@@ -194,6 +195,22 @@ pmc_start(pmc_state_t *pmc, struct x86_p
((args->flags & PMC_SETUP_INV) ? K7_EVTSEL_INV : 0) |
(args->compare << K7_EVTSEL_COUNTER_MASK_SHIFT);
break;
+
+ case PMC_TYPE_F10H:
+ event =
+ ((uint64_t)(args->event & 0x00FF) <<
+ F10H_EVTSEL_EVENT_SHIFT_LOW) |
+ ((uint64_t)(args->event & 0x0F00) <<
+ F10H_EVTSEL_EVENT_SHIFT_HIGH);
+ unit = (args->unit << F10H_EVTSEL_UNIT_SHIFT) &
+ F10H_EVTSEL_UNIT_MASK;
+ pmc->evtval = event | unit | F10H_EVTSEL_EN |
+ ((args->flags & PMC_SETUP_KERNEL) ? F10H_EVTSEL_OS : 0) |
+ ((args->flags & PMC_SETUP_USER) ? F10H_EVTSEL_USR : 0) |
+ ((args->flags & PMC_SETUP_EDGE) ? F10H_EVTSEL_EDGE : 0) |
+ ((args->flags & PMC_SETUP_INV) ? F10H_EVTSEL_INV : 0) |
+ (args->compare << F10H_EVTSEL_COUNTER_MASK_SHIFT);
+ break;
}
/*
@@ -245,17 +262,30 @@ pmc_init(void)
pmc_state[1].evtmsr = MSR_EVNTSEL1;
pmc_state[1].ctrmsr = MSR_PERFCTR1;
} else if (strncmp(cpu_vendorstr, "AuthenticAMD", 12) == 0) {
- /* XXX: make sure it is at least K7 */
- pmc_type = PMC_TYPE_K7;
- pmc_ncounters = 4;
- pmc_state[0].evtmsr = MSR_K7_EVNTSEL0;
- pmc_state[0].ctrmsr = MSR_K7_PERFCTR0;
- pmc_state[1].evtmsr = MSR_K7_EVNTSEL1;
- pmc_state[1].ctrmsr = MSR_K7_PERFCTR1;
- pmc_state[2].evtmsr = MSR_K7_EVNTSEL2;
- pmc_state[2].ctrmsr = MSR_K7_PERFCTR2;
- pmc_state[3].evtmsr = MSR_K7_EVNTSEL3;
- pmc_state[3].ctrmsr = MSR_K7_PERFCTR3;
+ if (CPUID_TO_FAMILY(ci->ci_signature) == 0x10) {
+ pmc_type = PMC_TYPE_F10H;
+ pmc_ncounters = 4;
+ pmc_state[0].evtmsr = MSR_F10H_EVNTSEL0;
+ pmc_state[0].ctrmsr = MSR_F10H_PERFCTR0;
+ pmc_state[1].evtmsr = MSR_F10H_EVNTSEL1;
+ pmc_state[1].ctrmsr = MSR_F10H_PERFCTR1;
+ pmc_state[2].evtmsr = MSR_F10H_EVNTSEL2;
+ pmc_state[2].ctrmsr = MSR_F10H_PERFCTR2;
+ pmc_state[3].evtmsr = MSR_F10H_EVNTSEL3;
+ pmc_state[3].ctrmsr = MSR_F10H_PERFCTR3;
+ } else {
+ /* XXX: make sure it is at least K7 */
+ pmc_type = PMC_TYPE_K7;
+ pmc_ncounters = 4;
+ pmc_state[0].evtmsr = MSR_K7_EVNTSEL0;
+ pmc_state[0].ctrmsr = MSR_K7_PERFCTR0;
+ pmc_state[1].evtmsr = MSR_K7_EVNTSEL1;
+ pmc_state[1].ctrmsr = MSR_K7_PERFCTR1;
+ pmc_state[2].evtmsr = MSR_K7_EVNTSEL2;
+ pmc_state[2].ctrmsr = MSR_K7_PERFCTR2;
+ pmc_state[3].evtmsr = MSR_K7_EVNTSEL3;
+ pmc_state[3].ctrmsr = MSR_K7_PERFCTR3;
+ }
}
break;
}
@@ -268,6 +298,8 @@ sys_pmc_info(struct lwp *l, struct x86_p
{
struct x86_pmc_info_args rv;
+printf("PMCTYPE: %d\n", (int)pmc_type);
+
memset(&rv, 0, sizeof(rv));
rv.vers = PMC_VERSION;
Index: src/usr.bin/pmc/pmc.c
diff -u src/usr.bin/pmc/pmc.c:1.21 src/usr.bin/pmc/pmc.c:1.22
--- src/usr.bin/pmc/pmc.c:1.21 Fri Mar 10 15:06:20 2017
+++ src/usr.bin/pmc/pmc.c Sat Mar 11 10:33:46 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: pmc.c,v 1.21 2017/03/10 15:06:20 maxv Exp $ */
+/* $NetBSD: pmc.c,v 1.22 2017/03/11 10:33:46 maxv Exp $ */
/*
* Copyright (c) 2017 The NetBSD Foundation, Inc.
@@ -66,7 +66,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: pmc.c,v 1.21 2017/03/10 15:06:20 maxv Exp $");
+__RCSID("$NetBSD: pmc.c,v 1.22 2017/03/11 10:33:46 maxv Exp $");
#endif
#include <inttypes.h>
@@ -275,15 +275,6 @@ static const pmc_name2val_t i686_names[]
};
static const pmc_name2val_t k7_names[] = {
- { "seg-load-all", K7_SEGMENT_REG_LOADS, 0x7f },
- { "seg-load-es", K7_SEGMENT_REG_LOADS, 0x01 },
- { "seg-load-cs", K7_SEGMENT_REG_LOADS, 0x02 },
- { "seg-load-ss", K7_SEGMENT_REG_LOADS, 0x04 },
- { "seg-load-ds", K7_SEGMENT_REG_LOADS, 0x08 },
- { "seg-load-fs", K7_SEGMENT_REG_LOADS, 0x10 },
- { "seg-load-gs", K7_SEGMENT_REG_LOADS, 0x20 },
- { "seg-load-hs", K7_SEGMENT_REG_LOADS, 0x40 },
- { "seg-load-stall", K7_SEGMENT_LOAD_STALL, 0 },
{ "l1cache-access", K7_DATA_CACHE_ACCESS, 0 },
{ "l1cache-miss", K7_DATA_CACHE_MISS, 0 },
{ "l1cache-refill", K7_DATA_CACHE_REFILL, 0x1f },
@@ -304,36 +295,18 @@ static const pmc_name2val_t k7_names[] =
{ "l1cache-writeback-exclusive",K7_DATA_CACHE_WBACK, 0x04 },
{ "l1cache-writeback-owner", K7_DATA_CACHE_WBACK, 0x08 },
{ "l1cache-writeback-modified", K7_DATA_CACHE_WBACK, 0x10 },
- { "l2cache-access", K7_L2_REQUEST, 0xff },
- { "l2cache-tag-read", K7_L2_REQUEST, 0x01 },
- { "l2cache-tag-write", K7_L2_REQUEST, 0x02 },
- { "l2cache-inst-read", K7_L2_REQUEST, 0x04 },
- { "l2cache-inst-load", K7_L2_REQUEST, 0x08 },
- { "l2cache-data-store", K7_L2_REQUEST, 0x10 },
- { "l2cache-data-loadmem", K7_L2_REQUEST, 0x20 },
- { "l2cache-data-write", K7_L2_REQUEST, 0x40 },
- { "l2cache-data-move", K7_L2_REQUEST, 0x80 },
- { "l2cache-access-busy", K7_L2_REQUEST_BUSY, 0 },
- { "l2cache-hit", K7_L2_DTLB_HIT, 0 },
- { "l2cache-miss", K7_L2_DTLB_MISS, 0 },
+ { "l1DTLB-miss", K7_L1_DTLB_MISS, 0 },
+ { "l2DTLB-miss", K7_L2_DTLB_MISS, 0 },
+ { "l1ITLB-miss", K7_L1_ITLB_MISS, 0 },
+ { "l2ITLB-miss", K7_L2_ITLB_MISS, 0 },
{ "mem-misalign-ref", K7_MISALIGNED_DATA_REF, 0 },
- { "mem-access", K7_SYSTEM_REQUEST, 0 },
- { "mem-access-uc", K7_SYSTEM_REQUEST_TYPE, 0x01 },
- { "mem-access-wc", K7_SYSTEM_REQUEST_TYPE, 0x04 },
- { "mem-access-wt", K7_SYSTEM_REQUEST_TYPE, 0x10 },
- { "mem-access-wp", K7_SYSTEM_REQUEST_TYPE, 0x20 },
- { "mem-access-wb", K7_SYSTEM_REQUEST_TYPE, 0x40 },
{ "ins-fetch", K7_IFU_IFETCH, 0 },
{ "ins-fetch-miss", K7_IFU_IFETCH_MISS, 0 },
{ "ins-refill-l2", K7_IFU_REFILL_FROM_L2, 0 },
- { "ins-refill-mem", K7_IFU_REFILL_FROM_SYSTEM, 0 },
- { "ins-fetch-stall", K7_IFU_STALL, 0 },
+ { "ins-refill-sys", K7_IFU_REFILL_FROM_SYSTEM, 0 },
{ "ins-retired", K7_RETIRED_INST, 0 },
- { "ins-empty", K7_INSTRUCTION_DECODER_EMPTY, 0 },
- { "itlb-miss-l1", K7_ITLB_L1_MISS, 0 },
- { "itlb-miss-l2", K7_ITLB_L2_MISS, 0 },
{ "ops-retired", K7_RETIRED_OPS, 0 },
- { "branch-retired", K7_RETIRED_BRANCHES, 0 },
+ { "branch-retired", K7_RETIRED_BRANCH, 0 },
{ "branch-miss-retired", K7_RETIRED_BRANCH_MISPREDICTED, 0 },
{ "branch-taken-retired", K7_RETIRED_TAKEN_BRANCH, 0 },
{ "branch-taked-miss-retired",
@@ -341,19 +314,84 @@ static const pmc_name2val_t k7_names[] =
{ "branch-far-retired",
K7_RETIRED_FAR_CONTROL_TRANSFER, 0 },
{ "branch-resync-retired", K7_RETIRED_RESYNC_BRANCH, 0 },
- { "branch-near-retired", K7_RETIRED_NEAR_RETURNS, 0 },
- { "branch-near-miss-retired",
- K7_RETIRED_NEAR_RETURNS_MISPREDICTED, 0 },
- { "branch-indirect-miss-retired",
- K7_RETIRED_INDIRECT_MISPREDICTED, 0 },
{ "int-hw", K7_HW_INTR_RECV, 0 },
{ "int-cycles-masked", K7_CYCLES_INT_MASKED, 0 },
{ "int-cycles-masked-pending",
K7_CYCLES_INT_PENDING_AND_MASKED, 0 },
- { "break-match0", K7_BP0_MATCH, 0 },
- { "break-match1", K7_BP1_MATCH, 0 },
- { "break-match2", K7_BP2_MATCH, 0 },
- { "break-match3", K7_BP3_MATCH, 0 },
+};
+
+static const pmc_name2val_t f10h_names[] = {
+ { "seg-load-all", F10H_SEGMENT_REG_LOADS, 0x7f },
+ { "seg-load-es", F10H_SEGMENT_REG_LOADS, 0x01 },
+ { "seg-load-cs", F10H_SEGMENT_REG_LOADS, 0x02 },
+ { "seg-load-ss", F10H_SEGMENT_REG_LOADS, 0x04 },
+ { "seg-load-ds", F10H_SEGMENT_REG_LOADS, 0x08 },
+ { "seg-load-fs", F10H_SEGMENT_REG_LOADS, 0x10 },
+ { "seg-load-gs", F10H_SEGMENT_REG_LOADS, 0x20 },
+ { "seg-load-hs", F10H_SEGMENT_REG_LOADS, 0x40 },
+ { "l1cache-access", F10H_DATA_CACHE_ACCESS, 0 },
+ { "l1cache-miss", F10H_DATA_CACHE_MISS, 0 },
+ { "l1cache-refill", F10H_DATA_CACHE_REFILL_FROM_L2, 0x1f },
+ { "l1cache-refill-invalid", F10H_DATA_CACHE_REFILL_FROM_L2, 0x01 },
+ { "l1cache-refill-shared", F10H_DATA_CACHE_REFILL_FROM_L2, 0x02 },
+ { "l1cache-refill-exclusive", F10H_DATA_CACHE_REFILL_FROM_L2, 0x04 },
+ { "l1cache-refill-owner", F10H_DATA_CACHE_REFILL_FROM_L2, 0x08 },
+ { "l1cache-refill-modified", F10H_DATA_CACHE_REFILL_FROM_L2, 0x10 },
+ { "l1cache-load", F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x1f },
+ { "l1cache-load-invalid", F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x01 },
+ { "l1cache-load-shared", F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x02 },
+ { "l1cache-load-exclusive", F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x04 },
+ { "l1cache-load-owner", F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x08 },
+ { "l1cache-load-modified", F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x10 },
+ { "l1cache-writeback", F10H_CACHE_LINES_EVICTED, 0x1f },
+ { "l1cache-writeback-invalid", F10H_CACHE_LINES_EVICTED, 0x01 },
+ { "l1cache-writeback-shared", F10H_CACHE_LINES_EVICTED, 0x02 },
+ { "l1cache-writeback-exclusive",F10H_CACHE_LINES_EVICTED, 0x04 },
+ { "l1cache-writeback-owner", F10H_CACHE_LINES_EVICTED, 0x08 },
+ { "l1cache-writeback-modified", F10H_CACHE_LINES_EVICTED, 0x10 },
+ { "l1DTLB-hit-all", F10H_L1_DTLB_HIT, 0x07 },
+ { "l1DTLB-hit-4Kpage", F10H_L1_DTLB_HIT, 0x01 },
+ { "l1DTLB-hit-2Mpage", F10H_L1_DTLB_HIT, 0x02 },
+ { "l1DTLB-hit-1Gpage", F10H_L1_DTLB_HIT, 0x04 },
+ { "l1DTLB-miss-all", F10H_L1_DTLB_MISS, 0x07 },
+ { "l1DTLB-miss-4Kpage", F10H_L1_DTLB_MISS, 0x01 },
+ { "l1DTLB-miss-2Mpage", F10H_L1_DTLB_MISS, 0x02 },
+ { "l1DTLB-miss-1Gpage", F10H_L1_DTLB_MISS, 0x04 },
+ { "l2DTLB-miss-all", F10H_L2_DTLB_MISS, 0x03 },
+ { "l2DTLB-miss-4Kpage", F10H_L2_DTLB_MISS, 0x01 },
+ { "l2DTLB-miss-2Mpage", F10H_L2_DTLB_MISS, 0x02 },
+ /* l2DTLB-miss-1Gpage: reserved on some revisions, so disabled */
+ { "l1ITLB-miss", F10H_L1_ITLB_MISS, 0 },
+ { "l2ITLB-miss-all", F10H_L2_ITLB_MISS, 0x03 },
+ { "l2ITLB-miss-4Kpage", F10H_L2_ITLB_MISS, 0x01 },
+ { "l2ITLB-miss-2Mpage", F10H_L2_ITLB_MISS, 0x02 },
+ { "mem-misalign-ref", F10H_MISALIGNED_ACCESS, 0 },
+ { "ins-fetch", F10H_INSTRUCTION_CACHE_FETCH, 0 },
+ { "ins-fetch-miss", F10H_INSTRUCTION_CACHE_MISS, 0 },
+ { "ins-refill-l2", F10H_INSTRUCTION_CACHE_REFILL_FROM_L2, 0 },
+ { "ins-refill-sys", F10H_INSTRUCTION_CACHE_REFILL_FROM_SYS, 0 },
+ { "ins-fetch-stall", F10H_INSTRUCTION_FETCH_STALL, 0 },
+ { "ins-retired", F10H_RETIRED_INSTRUCTIONS, 0 },
+ { "ins-empty", F10H_DECODER_EMPTY, 0 },
+ { "ops-retired", F10H_RETIRED_UOPS, 0 },
+ { "branch-retired", F10H_RETIRED_BRANCH, 0 },
+ { "branch-miss-retired", F10H_RETIRED_MISPREDICTED_BRANCH,0 },
+ { "branch-taken-retired", F10H_RETIRED_TAKEN_BRANCH, 0 },
+ { "branch-taken-miss-retired", F10H_RETIRED_TAKEN_BRANCH_MISPREDICTED, 0 },
+ { "branch-far-retired", F10H_RETIRED_FAR_CONTROL_TRANSFER, 0 },
+ { "branch-resync-retired", F10H_RETIRED_BRANCH_RESYNC, 0 },
+ { "branch-near-retired", F10H_RETIRED_NEAR_RETURNS, 0 },
+ { "branch-near-miss-retired", F10H_RETIRED_NEAR_RETURNS_MISPREDICTED, 0 },
+ { "branch-indirect-miss-retired", F10H_RETIRED_INDIRECT_BRANCH_MISPREDICTED, 0 },
+ { "int-hw", F10H_INTERRUPTS_TAKEN, 0 },
+ { "int-cycles-masked", F10H_INTERRUPTS_MASKED_CYCLES, 0 },
+ { "int-cycles-masked-pending",
+ F10H_INTERRUPTS_MASKED_CYCLES_INTERRUPT_PENDING, 0 },
+ { "fpu-exceptions", F10H_FPU_EXCEPTIONS, 0 },
+ { "break-match0", F10H_DR0_BREAKPOINT_MATCHES, 0 },
+ { "break-match1", F10H_DR1_BREAKPOINT_MATCHES, 0 },
+ { "break-match2", F10H_DR2_BREAKPOINT_MATCHES, 0 },
+ { "break-match3", F10H_DR3_BREAKPOINT_MATCHES, 0 },
};
static const pmc_name2val_cpu_t pmc_cpus[] = {
@@ -363,6 +401,8 @@ static const pmc_name2val_cpu_t pmc_cpus
sizeof(i686_names) / sizeof(pmc_name2val_t) },
{ PMC_TYPE_K7, k7_names,
sizeof(k7_names) / sizeof(pmc_name2val_t) },
+ { PMC_TYPE_F10H, f10h_names,
+ sizeof(f10h_names) / sizeof(pmc_name2val_t) },
};
/* -------------------------------------------------------------------------- */
@@ -409,18 +449,17 @@ static void usage(void)
static void
pmc_list(const pmc_name2val_cpu_t *pncp, char **argv)
{
- int i, n, left, pairs;
+ size_t i, n, mid;
printf("Supported performance counter events:\n");
n = pncp->size;
- pairs = n / 2;
- left = n % 2;
+ mid = n / 2;
- for (i = 0; i < pairs; i++)
- printf(" %37s %37s\n", pncp->pmc_names[i * 2].name,
- pncp->pmc_names[i * 2 + 1].name);
- if (left != 0)
- printf("\t%37s\n", pncp->pmc_names[n - 1].name);
+ for (i = 0; i < mid; i++)
+ printf(" %-37s %-37s\n", pncp->pmc_names[i].name,
+ pncp->pmc_names[mid + i].name);
+ if ((n % 2) != 0)
+ printf(" %-37s\n", pncp->pmc_names[n - 1].name);
}
static void
