Module Name: src
Committed By: msaitoh
Date: Tue Mar 28 10:25:11 UTC 2017
Modified Files:
src/sys/dev/pci: pcireg.h
Log Message:
Indent. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.123 -r1.124 src/sys/dev/pci/pcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.123 src/sys/dev/pci/pcireg.h:1.124
--- src/sys/dev/pci/pcireg.h:1.123 Tue Mar 28 10:23:40 2017
+++ src/sys/dev/pci/pcireg.h Tue Mar 28 10:25:11 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.123 2017/03/28 10:23:40 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.124 2017/03/28 10:25:11 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -42,24 +42,24 @@
* Size of each function's configuration space.
*/
-#define PCI_CONF_SIZE 0x100
-#define PCI_EXTCONF_SIZE 0x1000
+#define PCI_CONF_SIZE 0x100
+#define PCI_EXTCONF_SIZE 0x1000
/*
* Device identification register; contains a vendor ID and a device ID.
*/
-#define PCI_ID_REG 0x00
+#define PCI_ID_REG 0x00
typedef u_int16_t pci_vendor_id_t;
typedef u_int16_t pci_product_id_t;
-#define PCI_VENDOR_SHIFT 0
-#define PCI_VENDOR_MASK 0xffff
+#define PCI_VENDOR_SHIFT 0
+#define PCI_VENDOR_MASK 0xffff
#define PCI_VENDOR(id) \
(((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
-#define PCI_PRODUCT_SHIFT 16
-#define PCI_PRODUCT_MASK 0xffff
+#define PCI_PRODUCT_SHIFT 16
+#define PCI_PRODUCT_MASK 0xffff
#define PCI_PRODUCT(id) \
(((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
@@ -70,72 +70,72 @@ typedef u_int16_t pci_product_id_t;
/*
* Command and status register.
*/
-#define PCI_COMMAND_STATUS_REG 0x04
-#define PCI_COMMAND_SHIFT 0
-#define PCI_COMMAND_MASK 0xffff
-#define PCI_STATUS_SHIFT 16
-#define PCI_STATUS_MASK 0xffff
+#define PCI_COMMAND_STATUS_REG 0x04
+#define PCI_COMMAND_SHIFT 0
+#define PCI_COMMAND_MASK 0xffff
+#define PCI_STATUS_SHIFT 16
+#define PCI_STATUS_MASK 0xffff
#define PCI_COMMAND_STATUS_CODE(cmd,stat) \
((((cmd) & PCI_COMMAND_MASK) << PCI_COMMAND_SHIFT) | \
(((stat) & PCI_STATUS_MASK) << PCI_STATUS_SHIFT)) \
-#define PCI_COMMAND_IO_ENABLE 0x00000001
-#define PCI_COMMAND_MEM_ENABLE 0x00000002
-#define PCI_COMMAND_MASTER_ENABLE 0x00000004
-#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008
-#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010
-#define PCI_COMMAND_PALETTE_ENABLE 0x00000020
-#define PCI_COMMAND_PARITY_ENABLE 0x00000040
-#define PCI_COMMAND_STEPPING_ENABLE 0x00000080
-#define PCI_COMMAND_SERR_ENABLE 0x00000100
-#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200
-#define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400
-
-#define PCI_STATUS_IMMD_READNESS __BIT(0+16)
-#define PCI_STATUS_INT_STATUS 0x00080000
-#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000
-#define PCI_STATUS_66MHZ_SUPPORT 0x00200000
-#define PCI_STATUS_UDF_SUPPORT 0x00400000
-#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000
-#define PCI_STATUS_PARITY_ERROR 0x01000000
-#define PCI_STATUS_DEVSEL_FAST 0x00000000
-#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000
-#define PCI_STATUS_DEVSEL_SLOW 0x04000000
-#define PCI_STATUS_DEVSEL_MASK 0x06000000
-#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000
-#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000
-#define PCI_STATUS_MASTER_ABORT 0x20000000
-#define PCI_STATUS_SPECIAL_ERROR 0x40000000
-#define PCI_STATUS_PARITY_DETECT 0x80000000
+#define PCI_COMMAND_IO_ENABLE 0x00000001
+#define PCI_COMMAND_MEM_ENABLE 0x00000002
+#define PCI_COMMAND_MASTER_ENABLE 0x00000004
+#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008
+#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010
+#define PCI_COMMAND_PALETTE_ENABLE 0x00000020
+#define PCI_COMMAND_PARITY_ENABLE 0x00000040
+#define PCI_COMMAND_STEPPING_ENABLE 0x00000080
+#define PCI_COMMAND_SERR_ENABLE 0x00000100
+#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200
+#define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400
+
+#define PCI_STATUS_IMMD_READNESS __BIT(0+16)
+#define PCI_STATUS_INT_STATUS 0x00080000
+#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000
+#define PCI_STATUS_66MHZ_SUPPORT 0x00200000
+#define PCI_STATUS_UDF_SUPPORT 0x00400000
+#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000
+#define PCI_STATUS_PARITY_ERROR 0x01000000
+#define PCI_STATUS_DEVSEL_FAST 0x00000000
+#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000
+#define PCI_STATUS_DEVSEL_SLOW 0x04000000
+#define PCI_STATUS_DEVSEL_MASK 0x06000000
+#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000
+#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000
+#define PCI_STATUS_MASTER_ABORT 0x20000000
+#define PCI_STATUS_SPECIAL_ERROR 0x40000000
+#define PCI_STATUS_PARITY_DETECT 0x80000000
/*
* PCI Class and Revision Register; defines type and revision of device.
*/
-#define PCI_CLASS_REG 0x08
+#define PCI_CLASS_REG 0x08
typedef u_int8_t pci_class_t;
typedef u_int8_t pci_subclass_t;
typedef u_int8_t pci_interface_t;
typedef u_int8_t pci_revision_t;
-#define PCI_CLASS_SHIFT 24
-#define PCI_CLASS_MASK 0xff
+#define PCI_CLASS_SHIFT 24
+#define PCI_CLASS_MASK 0xff
#define PCI_CLASS(cr) \
(((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
-#define PCI_SUBCLASS_SHIFT 16
-#define PCI_SUBCLASS_MASK 0xff
+#define PCI_SUBCLASS_SHIFT 16
+#define PCI_SUBCLASS_MASK 0xff
#define PCI_SUBCLASS(cr) \
(((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
-#define PCI_INTERFACE_SHIFT 8
-#define PCI_INTERFACE_MASK 0xff
+#define PCI_INTERFACE_SHIFT 8
+#define PCI_INTERFACE_MASK 0xff
#define PCI_INTERFACE(cr) \
(((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
-#define PCI_REVISION_SHIFT 0
-#define PCI_REVISION_MASK 0xff
+#define PCI_REVISION_SHIFT 0
+#define PCI_REVISION_MASK 0xff
#define PCI_REVISION(cr) \
(((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
@@ -145,27 +145,27 @@ typedef u_int8_t pci_revision_t;
(((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT))
/* base classes */
-#define PCI_CLASS_PREHISTORIC 0x00
-#define PCI_CLASS_MASS_STORAGE 0x01
-#define PCI_CLASS_NETWORK 0x02
-#define PCI_CLASS_DISPLAY 0x03
-#define PCI_CLASS_MULTIMEDIA 0x04
-#define PCI_CLASS_MEMORY 0x05
-#define PCI_CLASS_BRIDGE 0x06
-#define PCI_CLASS_COMMUNICATIONS 0x07
-#define PCI_CLASS_SYSTEM 0x08
-#define PCI_CLASS_INPUT 0x09
-#define PCI_CLASS_DOCK 0x0a
-#define PCI_CLASS_PROCESSOR 0x0b
-#define PCI_CLASS_SERIALBUS 0x0c
-#define PCI_CLASS_WIRELESS 0x0d
-#define PCI_CLASS_I2O 0x0e
-#define PCI_CLASS_SATCOM 0x0f
-#define PCI_CLASS_CRYPTO 0x10
-#define PCI_CLASS_DASP 0x11
-#define PCI_CLASS_ACCEL 0x12
-#define PCI_CLASS_INSTRUMENT 0x13
-#define PCI_CLASS_UNDEFINED 0xff
+#define PCI_CLASS_PREHISTORIC 0x00
+#define PCI_CLASS_MASS_STORAGE 0x01
+#define PCI_CLASS_NETWORK 0x02
+#define PCI_CLASS_DISPLAY 0x03
+#define PCI_CLASS_MULTIMEDIA 0x04
+#define PCI_CLASS_MEMORY 0x05
+#define PCI_CLASS_BRIDGE 0x06
+#define PCI_CLASS_COMMUNICATIONS 0x07
+#define PCI_CLASS_SYSTEM 0x08
+#define PCI_CLASS_INPUT 0x09
+#define PCI_CLASS_DOCK 0x0a
+#define PCI_CLASS_PROCESSOR 0x0b
+#define PCI_CLASS_SERIALBUS 0x0c
+#define PCI_CLASS_WIRELESS 0x0d
+#define PCI_CLASS_I2O 0x0e
+#define PCI_CLASS_SATCOM 0x0f
+#define PCI_CLASS_CRYPTO 0x10
+#define PCI_CLASS_DASP 0x11
+#define PCI_CLASS_ACCEL 0x12
+#define PCI_CLASS_INSTRUMENT 0x13
+#define PCI_CLASS_UNDEFINED 0xff
/* 0x00 prehistoric subclasses */
#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
@@ -384,15 +384,15 @@ typedef u_int8_t pci_revision_t;
/*
* PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
*/
-#define PCI_BHLC_REG 0x0c
+#define PCI_BHLC_REG 0x0c
-#define PCI_BIST_SHIFT 24
-#define PCI_BIST_MASK 0xff
+#define PCI_BIST_SHIFT 24
+#define PCI_BIST_MASK 0xff
#define PCI_BIST(bhlcr) \
(((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
-#define PCI_HDRTYPE_SHIFT 16
-#define PCI_HDRTYPE_MASK 0xff
+#define PCI_HDRTYPE_SHIFT 16
+#define PCI_HDRTYPE_MASK 0xff
#define PCI_HDRTYPE(bhlcr) \
(((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
@@ -401,13 +401,13 @@ typedef u_int8_t pci_revision_t;
#define PCI_HDRTYPE_MULTIFN(bhlcr) \
((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
-#define PCI_LATTIMER_SHIFT 8
-#define PCI_LATTIMER_MASK 0xff
+#define PCI_LATTIMER_SHIFT 8
+#define PCI_LATTIMER_MASK 0xff
#define PCI_LATTIMER(bhlcr) \
(((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
-#define PCI_CACHELINE_SHIFT 0
-#define PCI_CACHELINE_MASK 0xff
+#define PCI_CACHELINE_SHIFT 0
+#define PCI_CACHELINE_MASK 0xff
#define PCI_CACHELINE(bhlcr) \
(((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
@@ -431,11 +431,11 @@ typedef u_int8_t pci_revision_t;
/*
* Mapping registers
*/
-#define PCI_MAPREG_START 0x10
-#define PCI_MAPREG_END 0x28
-#define PCI_MAPREG_ROM 0x30
-#define PCI_MAPREG_PPB_END 0x18
-#define PCI_MAPREG_PCB_END 0x14
+#define PCI_MAPREG_START 0x10
+#define PCI_MAPREG_END 0x28
+#define PCI_MAPREG_ROM 0x30
+#define PCI_MAPREG_PPB_END 0x18
+#define PCI_MAPREG_PCB_END 0x14
#define PCI_BAR0 0x10
#define PCI_BAR1 0x14
@@ -448,42 +448,42 @@ typedef u_int8_t pci_revision_t;
#define PCI_MAPREG_TYPE(mr) \
((mr) & PCI_MAPREG_TYPE_MASK)
-#define PCI_MAPREG_TYPE_MASK 0x00000001
+#define PCI_MAPREG_TYPE_MASK 0x00000001
-#define PCI_MAPREG_TYPE_MEM 0x00000000
-#define PCI_MAPREG_TYPE_ROM 0x00000000
-#define PCI_MAPREG_TYPE_IO 0x00000001
-#define PCI_MAPREG_ROM_ENABLE 0x00000001
+#define PCI_MAPREG_TYPE_MEM 0x00000000
+#define PCI_MAPREG_TYPE_ROM 0x00000000
+#define PCI_MAPREG_TYPE_IO 0x00000001
+#define PCI_MAPREG_ROM_ENABLE 0x00000001
#define PCI_MAPREG_MEM_TYPE(mr) \
((mr) & PCI_MAPREG_MEM_TYPE_MASK)
-#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006
+#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006
-#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000
-#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002
-#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
+#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000
+#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002
+#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \
(((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
-#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008
+#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008
#define PCI_MAPREG_MEM_ADDR(mr) \
((mr) & PCI_MAPREG_MEM_ADDR_MASK)
#define PCI_MAPREG_MEM_SIZE(mr) \
(PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
-#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
+#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
#define PCI_MAPREG_MEM64_ADDR(mr) \
((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
#define PCI_MAPREG_MEM64_SIZE(mr) \
(PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
-#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL
+#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL
#define PCI_MAPREG_IO_ADDR(mr) \
((mr) & PCI_MAPREG_IO_ADDR_MASK)
#define PCI_MAPREG_IO_SIZE(mr) \
(PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
-#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc
+#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc
#define PCI_MAPREG_SIZE_TO_MASK(size) \
(-(size))
@@ -495,16 +495,16 @@ typedef u_int8_t pci_revision_t;
/*
* Cardbus CIS pointer (PCI rev. 2.1)
*/
-#define PCI_CARDBUS_CIS_REG 0x28
+#define PCI_CARDBUS_CIS_REG 0x28
/*
* Subsystem identification register; contains a vendor ID and a device ID.
* Types/macros for PCI_ID_REG apply.
* (PCI rev. 2.1)
*/
-#define PCI_SUBSYS_ID_REG 0x2c
+#define PCI_SUBSYS_ID_REG 0x2c
-#define PCI_SUBSYS_VENDOR_MASK __BITS(15, 0)
+#define PCI_SUBSYS_VENDOR_MASK __BITS(15, 0)
#define PCI_SUBSYS_ID_MASK __BITS(31, 16)
#define PCI_SUBSYS_VENDOR(__subsys_id) \
@@ -516,8 +516,8 @@ typedef u_int8_t pci_revision_t;
/*
* Capabilities link list (PCI rev. 2.2)
*/
-#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */
-#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */
+#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */
+#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */
#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
@@ -1169,40 +1169,40 @@ struct pci_msix_table_entry {
/*
* Interrupt Configuration Register; contains interrupt pin and line.
*/
-#define PCI_INTERRUPT_REG 0x3c
+#define PCI_INTERRUPT_REG 0x3c
typedef u_int8_t pci_intr_latency_t;
typedef u_int8_t pci_intr_grant_t;
typedef u_int8_t pci_intr_pin_t;
typedef u_int8_t pci_intr_line_t;
-#define PCI_MAX_LAT_SHIFT 24
-#define PCI_MAX_LAT_MASK 0xff
+#define PCI_MAX_LAT_SHIFT 24
+#define PCI_MAX_LAT_MASK 0xff
#define PCI_MAX_LAT(icr) \
(((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)
-#define PCI_MIN_GNT_SHIFT 16
-#define PCI_MIN_GNT_MASK 0xff
+#define PCI_MIN_GNT_SHIFT 16
+#define PCI_MIN_GNT_MASK 0xff
#define PCI_MIN_GNT(icr) \
(((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)
-#define PCI_INTERRUPT_GRANT_SHIFT 24
-#define PCI_INTERRUPT_GRANT_MASK 0xff
+#define PCI_INTERRUPT_GRANT_SHIFT 24
+#define PCI_INTERRUPT_GRANT_MASK 0xff
#define PCI_INTERRUPT_GRANT(icr) \
(((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK)
-#define PCI_INTERRUPT_LATENCY_SHIFT 16
-#define PCI_INTERRUPT_LATENCY_MASK 0xff
+#define PCI_INTERRUPT_LATENCY_SHIFT 16
+#define PCI_INTERRUPT_LATENCY_MASK 0xff
#define PCI_INTERRUPT_LATENCY(icr) \
(((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK)
-#define PCI_INTERRUPT_PIN_SHIFT 8
-#define PCI_INTERRUPT_PIN_MASK 0xff
+#define PCI_INTERRUPT_PIN_SHIFT 8
+#define PCI_INTERRUPT_PIN_MASK 0xff
#define PCI_INTERRUPT_PIN(icr) \
(((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
-#define PCI_INTERRUPT_LINE_SHIFT 0
-#define PCI_INTERRUPT_LINE_MASK 0xff
+#define PCI_INTERRUPT_LINE_SHIFT 0
+#define PCI_INTERRUPT_LINE_MASK 0xff
#define PCI_INTERRUPT_LINE(icr) \
(((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)
@@ -1212,12 +1212,12 @@ typedef u_int8_t pci_intr_line_t;
(((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \
(((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT))
-#define PCI_INTERRUPT_PIN_NONE 0x00
-#define PCI_INTERRUPT_PIN_A 0x01
-#define PCI_INTERRUPT_PIN_B 0x02
-#define PCI_INTERRUPT_PIN_C 0x03
-#define PCI_INTERRUPT_PIN_D 0x04
-#define PCI_INTERRUPT_PIN_MAX 0x04
+#define PCI_INTERRUPT_PIN_NONE 0x00
+#define PCI_INTERRUPT_PIN_A 0x01
+#define PCI_INTERRUPT_PIN_B 0x02
+#define PCI_INTERRUPT_PIN_C 0x03
+#define PCI_INTERRUPT_PIN_D 0x04
+#define PCI_INTERRUPT_PIN_MAX 0x04
/* Header Type 1 (Bridge) configuration registers */
#define PCI_BRIDGE_BUS_REG 0x18
