Module Name: src
Committed By: nonaka
Date: Sat Apr 22 04:24:26 UTC 2017
Modified Files:
src/sys/arch/x86/include: i82489reg.h specialreg.h
src/sys/arch/x86/x86: lapic.c
Log Message:
move LAPIC_MSR* to specialreg.h.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/x86/include/i82489reg.h
cvs rdiff -u -r1.96 -r1.97 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.54 -r1.55 src/sys/arch/x86/x86/lapic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/i82489reg.h
diff -u src/sys/arch/x86/include/i82489reg.h:1.14 src/sys/arch/x86/include/i82489reg.h:1.15
--- src/sys/arch/x86/include/i82489reg.h:1.14 Sat Apr 22 04:23:17 2017
+++ src/sys/arch/x86/include/i82489reg.h Sat Apr 22 04:24:25 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: i82489reg.h,v 1.14 2017/04/22 04:23:17 nonaka Exp $ */
+/* $NetBSD: i82489reg.h,v 1.15 2017/04/22 04:24:25 nonaka Exp $ */
/*-
* Copyright (c) 1998, 2008 The NetBSD Foundation, Inc.
@@ -222,13 +222,3 @@
# define LEAPIC_LVTR_DSTAT __BIT(12) /* delivery state RO */
# define LEAPIC_LVTR_MSGTYPE __BITS(10,8) /* Message type */
# define LEAPIC_LVTR_VEC __BITS(7,0) /* the intr. vector */
-
-/*
- * Model specific registers
- */
-
-#define LAPIC_MSR 0x001b
-# define LAPIC_MSR_BSP 0x00000100 /* boot processor */
-# define LAPIC_MSR_ENABLE_x2 0x00000400 /* x2APIC mode */
-# define LAPIC_MSR_ENABLE 0x00000800 /* software enable */
-# define LAPIC_MSR_ADDR 0xfffff000 /* physical address */
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.96 src/sys/arch/x86/include/specialreg.h:1.97
--- src/sys/arch/x86/include/specialreg.h:1.96 Sat Apr 22 04:23:17 2017
+++ src/sys/arch/x86/include/specialreg.h Sat Apr 22 04:24:25 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.96 2017/04/22 04:23:17 nonaka Exp $ */
+/* $NetBSD: specialreg.h,v 1.97 2017/04/22 04:24:25 nonaka Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -551,6 +551,10 @@
#define MSR_CTR1 0x013 /* P5 only (trap on P6) */
#define MSR_IA32_PLATFORM_ID 0x017
#define MSR_APICBASE 0x01b
+#define APICBASE_BSP 0x00000100 /* boot processor */
+#define APICBASE_EXTD 0x00000400 /* x2APIC mode */
+#define APICBASE_EN 0x00000800 /* software enable */
+#define APICBASE_PHYSADDR 0xfffff000 /* physical address */
#define MSR_EBL_CR_POWERON 0x02a
#define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */
#define MSR_TEST_CTL 0x033
Index: src/sys/arch/x86/x86/lapic.c
diff -u src/sys/arch/x86/x86/lapic.c:1.54 src/sys/arch/x86/x86/lapic.c:1.55
--- src/sys/arch/x86/x86/lapic.c:1.54 Fri Nov 25 14:12:56 2016
+++ src/sys/arch/x86/x86/lapic.c Sat Apr 22 04:24:26 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: lapic.c,v 1.54 2016/11/25 14:12:56 maxv Exp $ */
+/* $NetBSD: lapic.c,v 1.55 2017/04/22 04:24:26 nonaka Exp $ */
/*-
* Copyright (c) 2000, 2008 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.54 2016/11/25 14:12:56 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.55 2017/04/22 04:24:26 nonaka Exp $");
#include "opt_ddb.h"
#include "opt_mpbios.h" /* for MPDEBUG */
@@ -103,12 +103,12 @@ lapic_map(paddr_t lapic_base)
* is not present on the Pentium (is it?).
*/
if (CPUID_TO_FAMILY(curcpu()->ci_signature) >= 6) {
- lapic_base = (paddr_t)rdmsr(LAPIC_MSR);
- if ((lapic_base & LAPIC_MSR_ADDR) == 0) {
- lapic_base |= LAPIC_BASE;
+ lapic_base = (paddr_t)rdmsr(MSR_APICBASE);
+ if ((lapic_base & APICBASE_PHYSADDR) == 0) {
+ lapic_base |= APICBASE_PHYSADDR;
}
- wrmsr(LAPIC_MSR, lapic_base | LAPIC_MSR_ENABLE);
- lapic_base &= LAPIC_MSR_ADDR;
+ wrmsr(MSR_APICBASE, lapic_base | APICBASE_EN);
+ lapic_base &= APICBASE_PHYSADDR;
}
x86_disable_intr();
