Module Name: src
Committed By: jmcneill
Date: Fri Apr 28 09:46:49 UTC 2017
Modified Files:
src/sys/arch/arm/nvidia: files.tegra tegra_xusb.c
Log Message:
Hide the debug output unless either TEGRA_XUSB_DEBUG is defined or
tegra_xusb_debug is set to 1.
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/nvidia/files.tegra
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/nvidia/tegra_xusb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/nvidia/files.tegra
diff -u src/sys/arch/arm/nvidia/files.tegra:1.33 src/sys/arch/arm/nvidia/files.tegra:1.34
--- src/sys/arch/arm/nvidia/files.tegra:1.33 Sun Apr 23 12:31:38 2017
+++ src/sys/arch/arm/nvidia/files.tegra Fri Apr 28 09:46:49 2017
@@ -1,4 +1,4 @@
-# $NetBSD: files.tegra,v 1.33 2017/04/23 12:31:38 jmcneill Exp $
+# $NetBSD: files.tegra,v 1.34 2017/04/28 09:46:49 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@@ -99,6 +99,7 @@ file arch/arm/nvidia/tegra_ehci.c tegra
# XUSB (USB 3.0)
attach xhci at fdt with tegra_xusb
file arch/arm/nvidia/tegra_xusb.c tegra_xusb
+defflag opt_tegra.h TEGRA_XUSB_DEBUG
# SDMMC
attach sdhc at fdt with tegra_sdhc
Index: src/sys/arch/arm/nvidia/tegra_xusb.c
diff -u src/sys/arch/arm/nvidia/tegra_xusb.c:1.5 src/sys/arch/arm/nvidia/tegra_xusb.c:1.6
--- src/sys/arch/arm/nvidia/tegra_xusb.c:1.5 Sun Apr 16 12:28:21 2017
+++ src/sys/arch/arm/nvidia/tegra_xusb.c Fri Apr 28 09:46:49 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_xusb.c,v 1.5 2017/04/16 12:28:21 jmcneill Exp $ */
+/* $NetBSD: tegra_xusb.c,v 1.6 2017/04/28 09:46:49 jmcneill Exp $ */
/*
* Copyright (c) 2016 Jonathan A. Kollasch
@@ -30,7 +30,7 @@
#include "opt_tegra.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.5 2017/04/16 12:28:21 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.6 2017/04/28 09:46:49 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -57,6 +57,14 @@ __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c
#include <dev/usb/xhcireg.h>
#include <dev/usb/xhcivar.h>
+#ifdef TEGRA_XUSB_DEBUG
+int tegra_xusb_debug = 1;
+#else
+int tegra_xusb_debug = 0;
+#endif
+
+#define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__)
+
static int tegra_xusb_match(device_t, cfdata_t, void *);
static void tegra_xusb_attach(device_t, device_t, void *);
static void tegra_xusb_mountroot(device_t);
@@ -126,10 +134,10 @@ tegra_xusb_attach(device_t parent, devic
char intrstr[128];
bus_addr_t addr;
bus_size_t size;
- int error;
+ struct fdtbus_reset *rst;
struct clk *clk;
uint32_t rate;
- struct fdtbus_reset *rst;
+ int error;
aprint_naive("\n");
aprint_normal(": XUSB\n");
@@ -149,7 +157,7 @@ tegra_xusb_attach(device_t parent, devic
aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
return;
}
- printf("mapped %#llx\n", (uint64_t)addr);
+ DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr);
if (fdtbus_get_reg(faa->faa_phandle, 1, &addr, &size) != 0) {
aprint_error(": couldn't get registers\n");
@@ -160,7 +168,7 @@ tegra_xusb_attach(device_t parent, devic
aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
return;
}
- printf("mapped %#llx\n", (uint64_t)addr);
+ DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr);
if (fdtbus_get_reg(faa->faa_phandle, 2, &addr, &size) != 0) {
aprint_error(": couldn't get registers\n");
@@ -171,7 +179,7 @@ tegra_xusb_attach(device_t parent, devic
aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
return;
}
- printf("mapped %#llx\n", (uint64_t)addr);
+ DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr);
if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
aprint_error_dev(self, "failed to decode interrupt\n");
@@ -204,40 +212,40 @@ tegra_xusb_attach(device_t parent, devic
clk = fdtbus_clock_get(faa->faa_phandle, "pll_e");
rate = clk_get_rate(clk);
error = clk_enable(clk); /* XXX set frequency */
- device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock");
clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src");
rate = clk_get_rate(clk);
- device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
error = clk_set_rate(clk, 102000000);
tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate");
rate = clk_get_rate(clk);
error = clk_enable(clk); /* XXX set frequency */
- device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock");
clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src");
rate = clk_get_rate(clk);
- device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
error = clk_set_rate(clk, 204000000);
tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate");
rate = clk_get_rate(clk);
error = clk_enable(clk);
- device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock");
clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host");
rate = clk_get_rate(clk);
error = clk_enable(clk); /* XXX set frequency */
- device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss");
rate = clk_get_rate(clk);
error = clk_enable(clk); /* XXX set frequency */
- device_printf(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error);
tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock");
psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src");
@@ -245,37 +253,36 @@ tegra_xusb_attach(device_t parent, devic
"failed to get xusb_ss_src clock");
rate = clk_get_rate(psc->sc_clk_ss_src);
- device_printf(sc->sc_dev, "xusb_ss_src rate %u\n", rate);
+ DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate);
error = clk_set_rate(psc->sc_clk_ss_src, 2000000);
rate = clk_get_rate(psc->sc_clk_ss_src);
- device_printf(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate,
- error);
+ DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error);
tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate");
rate = clk_get_rate(psc->sc_clk_ss_src);
- device_printf(sc->sc_dev, "ss_src rate %u\n", rate);
+ DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate);
tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate");
error = clk_set_rate(psc->sc_clk_ss_src, 120000000);
rate = clk_get_rate(psc->sc_clk_ss_src);
- device_printf(sc->sc_dev, "ss_src rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error);
tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate");
error = clk_enable(psc->sc_clk_ss_src);
- device_printf(sc->sc_dev, "ss_src rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error);
tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock");
#if 0
clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src");
error = 0;
rate = clk_get_rate(clk);
- device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
#endif
clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src");
rate = clk_get_rate(clk);
error = clk_enable(clk); /* XXX set frequency */
- device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock");
rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host");
@@ -311,29 +318,29 @@ tegra_xusb_mountroot(device_t self)
uint32_t val;
int error;
- device_printf(sc->sc_dev, "%s()\n", __func__);
+ DPRINTF(sc->sc_dev, "%s()\n", __func__);
val = bus_space_read_4(bst, ipfsh, 0x0);
- device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val);
+ DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val);
if (tegra_xusb_load_fw(psc) != 0)
return;
- device_printf(sc->sc_dev, "post fw\n");
+ DPRINTF(sc->sc_dev, "post fw\n");
tegra_xusbpad_xhci_enable();
clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src");
rate = clk_get_rate(clk);
error = clk_enable(clk);
- device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src");
rate = clk_get_rate(clk);
error = clk_enable(clk);
- device_printf(sc->sc_dev, "rate %u error %d\n", rate, error);
+ DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
val = bus_space_read_4(bst, ipfsh, 0x0);
- device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val);
+ DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val);
rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host");
fdtbus_reset_deassert(rst);
@@ -345,7 +352,7 @@ tegra_xusb_mountroot(device_t self)
fdtbus_reset_deassert(rst);
val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG);
- device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val);
+ DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val);
error = xhci_init(sc);
@@ -376,20 +383,20 @@ tegra_xusb_intr_mbox(void *v)
uint32_t msg;
int error;
- device_printf(sc->sc_dev, "%s()\n", __func__);
+ DPRINTF(sc->sc_dev, "%s()\n", __func__);
irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG);
- device_printf(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv);
+ DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv);
bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv);
if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG)
- device_printf(sc->sc_dev, "firmware hang\n");
+ aprint_error_dev(sc->sc_dev, "firmware hang\n");
msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG);
- device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg);
+ DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg);
val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG);
- device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val);
+ DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val);
val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI;
bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val);
@@ -402,19 +409,19 @@ tegra_xusb_intr_mbox(void *v)
switch (type) {
case 2:
case 3:
- device_printf(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000);
+ DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000);
break;
case 4:
case 5:
- device_printf(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000);
+ DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000);
rate = clk_get_rate(psc->sc_clk_ss_src);
- device_printf(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n",
+ DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n",
rate);
error = clk_set_rate(psc->sc_clk_ss_src, data * 1000);
if (error != 0)
goto clk_fail;
rate = clk_get_rate(psc->sc_clk_ss_src);
- device_printf(sc->sc_dev,
+ DPRINTF(sc->sc_dev,
"rate of psc->sc_clk_ss_src %u after\n", rate);
if (data == (rate / 1000)) {
msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) |
@@ -455,52 +462,52 @@ tegra_xusb_init(struct tegra_xusb_softc
const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs;
const bus_space_handle_t fpcih = psc->sc_bsh_fpci;
- device_printf(sc->sc_dev, "%s()\n", __func__);
+ DPRINTF(sc->sc_dev, "%s()\n", __func__);
- device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__,
+ DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__,
bus_space_read_4(bst, ipfsh, 0x0));
- device_printf(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__,
+ DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__,
bus_space_read_4(bst, ipfsh, 0x40));
- device_printf(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__,
+ DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__,
bus_space_read_4(bst, ipfsh, 0x80));
/* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */
bus_space_write_4(bst, ipfsh, 0x80, 0x00100000);
- device_printf(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__,
+ DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__,
bus_space_read_4(bst, ipfsh, 0x80));
- device_printf(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__,
+ DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__,
bus_space_read_4(bst, ipfsh, 0x180));
/* EN_FPCI */
tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0);
- device_printf(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__,
+ DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__,
bus_space_read_4(bst, ipfsh, 0x180));
- device_printf(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n",
+ DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n",
__func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG));
tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0);
- device_printf(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n",
+ DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n",
__func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG));
- device_printf(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__,
+ DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__,
bus_space_read_4(bst, fpcih, PCI_BAR0));
/* match FPCI BAR0 to above */
bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000);
- device_printf(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__,
+ DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__,
bus_space_read_4(bst, fpcih, PCI_BAR0));
- device_printf(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__,
+ DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__,
bus_space_read_4(bst, ipfsh, 0x188));
tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0);
- device_printf(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__,
+ DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__,
bus_space_read_4(bst, ipfsh, 0x188));
- device_printf(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__,
+ DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__,
bus_space_read_4(bst, fpcih, 0x1bc));
bus_space_write_4(bst, fpcih, 0x1bc, 0x80);
- device_printf(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__,
+ DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__,
bus_space_read_4(bst, fpcih, 0x1bc));
}
@@ -593,7 +600,7 @@ tegra_xusb_load_fw(struct tegra_xusb_sof
}
firmware_image = psc->sc_fw_dma.addr;
- device_printf(sc->sc_dev, "blob %p len %zu\n", firmware_image,
+ DPRINTF(sc->sc_dev, "blob %p len %zu\n", firmware_image,
firmware_size);
#if defined(TEGRA124_XUSB_BIN_STATIC)
@@ -615,22 +622,22 @@ tegra_xusb_load_fw(struct tegra_xusb_sof
const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]);
if (fwimg_len != firmware_size)
- device_printf(sc->sc_dev, "fwimg_len mismatch %u != %zu\n",
+ aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n",
fwimg_len, firmware_size);
bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0,
firmware_size, BUS_DMASYNC_PREWRITE);
- device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG));
- device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG));
- device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG));
csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG,
fwimg_len);
- device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG));
const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr +
@@ -638,24 +645,24 @@ tegra_xusb_load_fw(struct tegra_xusb_sof
csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32);
csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase);
- device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG));
- device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG));
- device_printf(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG));
csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG,
XUSB_CSB_MEMPOOL_APMAP_BOOTPATH);
- device_printf(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG));
- device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG));
csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG,
__SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL,
XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION));
- device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG));
const u_int code_tag_blocks =
@@ -664,56 +671,56 @@ tegra_xusb_load_fw(struct tegra_xusb_sof
howmany(boot_codesize, IMEM_BLOCK_SIZE);
const u_int code_blocks = code_tag_blocks + code_size_blocks;
- device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG));
csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG,
__SHIFTIN(code_tag_blocks,
XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) |
__SHIFTIN(code_size_blocks,
XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT));
- device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG));
- device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG));
csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG,
__SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT,
XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION));
- device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG));
- device_printf(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n",
csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG));
csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks);
- device_printf(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n",
csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG));
- device_printf(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n",
csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG));
csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG,
__SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) |
__SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI));
- device_printf(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n",
csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG));
- device_printf(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n",
csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG));
csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0);
- device_printf(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n",
csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG));
- device_printf(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n",
csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG));
csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG,
boot_codetag);
- device_printf(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n",
csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG));
- device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG));
csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG,
XUSB_CSB_FALCON_CPUCTL_STARTCPU);
- device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG));
return 0;
@@ -758,7 +765,7 @@ xusb_mailbox_send(struct tegra_xusb_soft
if (!(type == 128 || type == 129)) {
val = bus_space_read_4(bst, fpcih,
T_XUSB_CFG_ARU_MAILBOX_OWNER_REG);
- device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n",
val);
if (val != MAILBOX_OWNER_NONE) {
return EBUSY;
@@ -769,7 +776,7 @@ xusb_mailbox_send(struct tegra_xusb_soft
val = bus_space_read_4(bst, fpcih,
T_XUSB_CFG_ARU_MAILBOX_OWNER_REG);
- device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n",
+ DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n",
val);
if (val != MAILBOX_OWNER_SW) {
return EBUSY;
@@ -789,7 +796,7 @@ xusb_mailbox_send(struct tegra_xusb_soft
for (u_int i = 0; i < 2500; i++) {
val = bus_space_read_4(bst, fpcih,
T_XUSB_CFG_ARU_MAILBOX_OWNER_REG);
- device_printf(sc->sc_dev,
+ DPRINTF(sc->sc_dev,
"XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val);
if (val == MAILBOX_OWNER_NONE) {
break;
@@ -799,10 +806,10 @@ xusb_mailbox_send(struct tegra_xusb_soft
val = bus_space_read_4(bst, fpcih,
T_XUSB_CFG_ARU_MAILBOX_OWNER_REG);
- device_printf(sc->sc_dev,
+ DPRINTF(sc->sc_dev,
"XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val);
if (val != MAILBOX_OWNER_NONE) {
- device_printf(sc->sc_dev,
+ aprint_error_dev(sc->sc_dev,
"timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val);
}
}
