Module Name: src
Committed By: msaitoh
Date: Mon May 15 04:02:52 UTC 2017
Modified Files:
src/sys/arch/x86/include: cpu.h specialreg.h
Log Message:
CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify comments
and snprintb() sring.
To generate a diff of this commit:
cvs rdiff -u -r1.69 -r1.70 src/sys/arch/x86/include/cpu.h
cvs rdiff -u -r1.97 -r1.98 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu.h
diff -u src/sys/arch/x86/include/cpu.h:1.69 src/sys/arch/x86/include/cpu.h:1.70
--- src/sys/arch/x86/include/cpu.h:1.69 Fri Apr 14 04:43:47 2017
+++ src/sys/arch/x86/include/cpu.h Mon May 15 04:02:52 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.69 2017/04/14 04:43:47 kamil Exp $ */
+/* $NetBSD: cpu.h,v 1.70 2017/05/15 04:02:52 msaitoh Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -180,7 +180,7 @@ struct cpu_info {
const struct cpu_functions *ci_func; /* start/stop functions */
struct trapframe *ci_ddb_regs;
- u_int ci_cflush_lsize; /* CFLUSH insn line size */
+ u_int ci_cflush_lsize; /* CLFLUSH insn line size */
struct x86_cache_info ci_cinfo[CAI_COUNT];
union descriptor *ci_gdt;
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.97 src/sys/arch/x86/include/specialreg.h:1.98
--- src/sys/arch/x86/include/specialreg.h:1.97 Sat Apr 22 04:24:25 2017
+++ src/sys/arch/x86/include/specialreg.h Mon May 15 04:02:52 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.97 2017/04/22 04:24:25 nonaka Exp $ */
+/* $NetBSD: specialreg.h,v 1.98 2017/05/15 04:02:52 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -144,7 +144,7 @@
#define CPUID_PAT 0x00010000 /* Page Attribute Table */
#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
#define CPUID_PN 0x00040000 /* processor serial number */
-#define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
+#define CPUID_CFLUSH 0x00080000 /* CLFLUSH insn supported */
#define CPUID_B20 0x00100000 /* reserved */
#define CPUID_DS 0x00200000 /* Debug Store */
#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
@@ -163,7 +163,7 @@
"\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \
"\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \
"\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \
- "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CFLUSH" \
+ "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \
"\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \
"\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \
"\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF"
