Module Name: src
Committed By: skrll
Date: Sun May 21 06:49:13 UTC 2017
Modified Files:
src/sys/arch/evbmips/ingenic: clock.c cpu.c intr.c machdep.c mainbus.c
src/sys/arch/mips/conf: files.ingenic
src/sys/arch/mips/ingenic: ingenic_regs.h ingenic_var.h
Added Files:
src/sys/arch/mips/ingenic: ingenic_coreregs.h
src/sys/arch/mips/mips: locore_ingenic.S
Log Message:
Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability.
While here convert some other M[TF]C0 uses to already exising accessor
functions, e.g. mipsNN_cp0_ebase_read
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/evbmips/ingenic/clock.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbmips/ingenic/cpu.c
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/evbmips/ingenic/intr.c
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/evbmips/ingenic/machdep.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/evbmips/ingenic/mainbus.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/conf/files.ingenic
cvs rdiff -u -r0 -r1.1 src/sys/arch/mips/ingenic/ingenic_coreregs.h
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/mips/ingenic/ingenic_regs.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/ingenic/ingenic_var.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/mips/mips/locore_ingenic.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbmips/ingenic/clock.c
diff -u src/sys/arch/evbmips/ingenic/clock.c:1.9 src/sys/arch/evbmips/ingenic/clock.c:1.10
--- src/sys/arch/evbmips/ingenic/clock.c:1.9 Fri May 19 07:40:58 2017
+++ src/sys/arch/evbmips/ingenic/clock.c Sun May 21 06:49:12 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: clock.c,v 1.9 2017/05/19 07:40:58 skrll Exp $ */
+/* $NetBSD: clock.c,v 1.10 2017/05/21 06:49:12 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.9 2017/05/19 07:40:58 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.10 2017/05/21 06:49:12 skrll Exp $");
#include "opt_multiprocessor.h"
@@ -38,6 +38,7 @@ __KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.
#include <sys/systm.h>
#include <sys/timetc.h>
+#include <mips/ingenic/ingenic_var.h>
#include <mips/ingenic/ingenic_regs.h>
#include "opt_ingenic.h"
@@ -236,7 +237,7 @@ ingenic_clockintr(struct clockframe *cf)
* XXX
* needs to take the IPI lock and ping all online CPUs, not just core 1
*/
- MTC0(1 << IPI_CLOCK, 20, 1);
+ mips_cp0_corembox_write(1, 1 << IPI_CLOCK);
#endif
hardclock(cf);
splx(s);
Index: src/sys/arch/evbmips/ingenic/cpu.c
diff -u src/sys/arch/evbmips/ingenic/cpu.c:1.3 src/sys/arch/evbmips/ingenic/cpu.c:1.4
--- src/sys/arch/evbmips/ingenic/cpu.c:1.3 Fri May 19 07:40:58 2017
+++ src/sys/arch/evbmips/ingenic/cpu.c Sun May 21 06:49:12 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.3 2017/05/19 07:40:58 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.4 2017/05/21 06:49:12 skrll Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2017/05/19 07:40:58 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.4 2017/05/21 06:49:12 skrll Exp $");
#include "opt_ingenic.h"
#include "opt_multiprocessor.h"
@@ -47,8 +47,9 @@ __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3
#include <sys/cpu.h>
#include <mips/locore.h>
-#include <mips/asm.h>
+#include <mips/ingenic/ingenic_coreregs.h>
#include <mips/ingenic/ingenic_regs.h>
+#include <mips/ingenic/ingenic_var.h>
static int cpu_match(device_t, cfdata_t, void *);
static void cpu_attach(device_t, device_t, void *);
@@ -85,14 +86,16 @@ cpu_attach(device_t parent, device_t sel
ci = startup_cpu_info;
wbflush();
vec = (uint32_t)&ingenic_wakeup;
- reg = MFC0(12, 4); /* reset entry reg */
+ reg = mips_cp0_corereim_read();
reg &= ~REIM_ENTRY_M;
reg |= vec;
- MTC0(reg, 12, 4);
- reg = MFC0(12, 2); /* core control reg */
+ mips_cp0_corereim_write(reg);
+
+ reg = mips_cp0_corectrl_read();
reg |= CC_RPC1; /* use our exception vector */
reg &= ~CC_SW_RST1; /* get core 1 out of reset */
- MTC0(reg, 12, 2);
+ mips_cp0_corectrl_write(reg);
+
while ((!kcpuset_isset(cpus_hatched, cpu_index(startup_cpu_info))) && (bail > 0)) {
delay(1000);
bail--;
Index: src/sys/arch/evbmips/ingenic/intr.c
diff -u src/sys/arch/evbmips/ingenic/intr.c:1.12 src/sys/arch/evbmips/ingenic/intr.c:1.13
--- src/sys/arch/evbmips/ingenic/intr.c:1.12 Sat Aug 27 05:52:43 2016
+++ src/sys/arch/evbmips/ingenic/intr.c Sun May 21 06:49:12 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.c,v 1.12 2016/08/27 05:52:43 skrll Exp $ */
+/* $NetBSD: intr.c,v 1.13 2017/05/21 06:49:12 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.12 2016/08/27 05:52:43 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.13 2017/05/21 06:49:12 skrll Exp $");
#define __INTR_PRIVATE
@@ -44,7 +44,9 @@ __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.1
#include <mips/locore.h>
#include <machine/intr.h>
+#include <mips/ingenic/ingenic_var.h>
#include <mips/ingenic/ingenic_regs.h>
+#include <mips/ingenic/ingenic_coreregs.h>
#include "opt_ingenic.h"
@@ -126,14 +128,15 @@ evbmips_intr_init(void)
writereg(JZ_ICMR1, 0xffffffff);
/* allow peripheral interrupts to core 0 only */
- reg = MFC0(12, 4); /* reset entry and interrupts */
+ reg = mips_cp0_corereim_read();
reg &= 0xffff0000;
reg |= REIM_IRQ0_M | REIM_MIRQ0_M;
#ifdef MULTIPROCESSOR
reg |= REIM_MIRQ1_M;
#endif
- MTC0(reg, 12, 4);
- MTC0(0, 20, 1); /* ping the 2nd core */
+ mips_cp0_corereim_write(reg);
+
+ mips_cp0_corembox_write(1, 0); /* ping the 2nd core */
DPRINTF("%s %08x\n", __func__, reg);
}
@@ -146,12 +149,12 @@ evbmips_iointr(int ipl, uint32_t ipendin
#if 0
snprintf(buffer, 256, "pending: %08x CR %08x\n", ipending,
- MFC0(MIPS_COP_0_CAUSE, 0));
+ mipsNN_cp0_cause_read());
ingenic_puts(buffer);
#endif
#endif
/* see which core we're on */
- id = MFC0(15, 1) & 7;
+ id = mipsNN_cp0_ebase_read() & 7;
/*
* XXX
@@ -166,12 +169,12 @@ evbmips_iointr(int ipl, uint32_t ipendin
int s = splsched();
/* read pending IPIs */
- reg = MFC0(12, 3);
+ reg = mips_cp0_corestatus_read();
if (id == 0) {
if (reg & CS_MIRQ0_P) {
#ifdef MULTIPROCESSOR
uint32_t tag;
- tag = MFC0(CP0_CORE_MBOX, 0);
+ tag = mips_cp0_corembox_read(id);
ipi_process(curcpu(), tag);
#ifdef INGENIC_INTR_DEBUG
@@ -182,13 +185,13 @@ evbmips_iointr(int ipl, uint32_t ipendin
#endif
reg &= (~CS_MIRQ0_P);
/* clear it */
- MTC0(reg, 12, 3);
+ mips_cp0_corestatus_write(reg);
}
} else if (id == 1) {
if (reg & CS_MIRQ1_P) {
#ifdef MULTIPROCESSOR
uint32_t tag;
- tag = MFC0(CP0_CORE_MBOX, 1);
+ tag = mips_cp0_corembox_read(id);
ingenic_puts("1");
if (tag & 0x400)
hardclock(cf);
@@ -201,7 +204,7 @@ evbmips_iointr(int ipl, uint32_t ipendin
#endif
reg &= (~CS_MIRQ1_P);
/* clear it */
- MTC0(reg, 12, 3);
+ mips_cp0_corestatus_write(reg);
}
}
splx(s);
Index: src/sys/arch/evbmips/ingenic/machdep.c
diff -u src/sys/arch/evbmips/ingenic/machdep.c:1.13 src/sys/arch/evbmips/ingenic/machdep.c:1.14
--- src/sys/arch/evbmips/ingenic/machdep.c:1.13 Fri May 19 07:40:58 2017
+++ src/sys/arch/evbmips/ingenic/machdep.c Sun May 21 06:49:12 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.13 2017/05/19 07:40:58 skrll Exp $ */
+/* $NetBSD: machdep.c,v 1.14 2017/05/21 06:49:12 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.13 2017/05/19 07:40:58 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.14 2017/05/21 06:49:12 skrll Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -61,6 +61,7 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v
#include <mips/locore.h>
#include <mips/cpuregs.h>
+#include <mips/ingenic/ingenic_coreregs.h>
#include <mips/ingenic/ingenic_regs.h>
#include <mips/ingenic/ingenic_var.h>
@@ -128,12 +129,12 @@ ingenic_cpu_init(struct cpu_info *ci)
uint32_t reg;
/* enable IPIs for this core */
- reg = MFC0(12, 4); /* reset entry and interrupts */
+ reg = mips_cp0_corereim_read();
if (cpu_index(ci) == 1) {
reg |= REIM_MIRQ1_M;
} else
reg |= REIM_MIRQ0_M;
- MTC0(reg, 12, 4);
+ mips_cp0_corereim_write(reg);
printf("%s %d %08x\n", __func__, cpu_index(ci), reg);
}
@@ -147,9 +148,9 @@ ingenic_send_ipi(struct cpu_info *ci, in
mutex_enter(&ingenic_ipi_lock);
if (kcpuset_isset(cpus_running, cpu_index(ci))) {
if (cpu_index(ci) == 0) {
- MTC0(msg, CP0_CORE_MBOX, 0);
+ mips_cp0_corembox_write(msg, 0);
} else {
- MTC0(msg, CP0_CORE_MBOX, 1);
+ mips_cp0_corembox_write(msg, 1);
}
}
mutex_exit(&ingenic_ipi_lock);
Index: src/sys/arch/evbmips/ingenic/mainbus.c
diff -u src/sys/arch/evbmips/ingenic/mainbus.c:1.6 src/sys/arch/evbmips/ingenic/mainbus.c:1.7
--- src/sys/arch/evbmips/ingenic/mainbus.c:1.6 Fri May 19 07:40:58 2017
+++ src/sys/arch/evbmips/ingenic/mainbus.c Sun May 21 06:49:12 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: mainbus.c,v 1.6 2017/05/19 07:40:58 skrll Exp $ */
+/* $NetBSD: mainbus.c,v 1.7 2017/05/21 06:49:12 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.6 2017/05/19 07:40:58 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.7 2017/05/21 06:49:12 skrll Exp $");
#include "opt_multiprocessor.h"
@@ -95,11 +95,11 @@ mainbus_attach(device_t parent, device_t
printf("TMR: %08x\n", readreg(JZ_TC_TMR));
/* send ourselves an IPI */
- MTC0(0x12345678, CP0_CORE_MBOX, 0);
+ mips_cp0_corembox_write(0x12345678, 0);
delay(1000);
/* send the other core an IPI */
- MTC0(0x12345678, CP0_CORE_MBOX, 1);
+ mips_cp0_corembox_write(0x12345678, 1);
delay(1000);
#endif
}
Index: src/sys/arch/mips/conf/files.ingenic
diff -u src/sys/arch/mips/conf/files.ingenic:1.9 src/sys/arch/mips/conf/files.ingenic:1.10
--- src/sys/arch/mips/conf/files.ingenic:1.9 Fri May 19 07:30:24 2017
+++ src/sys/arch/mips/conf/files.ingenic Sun May 21 06:49:13 2017
@@ -1,6 +1,7 @@
-# $NetBSD: files.ingenic,v 1.9 2017/05/19 07:30:24 skrll Exp $
+# $NetBSD: files.ingenic,v 1.10 2017/05/21 06:49:13 skrll Exp $
file arch/mips/mips/bus_dma.c
+file arch/mips/mips/locore_ingenic.S
include "dev/scsipi/files.scsipi" # SCSI devices
include "dev/ata/files.ata" # ATA devices
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.24 src/sys/arch/mips/ingenic/ingenic_regs.h:1.25
--- src/sys/arch/mips/ingenic/ingenic_regs.h:1.24 Sat Aug 27 05:56:33 2016
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Sun May 21 06:49:13 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.24 2016/08/27 05:56:33 skrll Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.25 2017/05/21 06:49:13 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -129,47 +129,6 @@ readreg(uint32_t reg)
return *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg);
}
-/* extra CP0 registers */
-static inline uint32_t
-MFC0(uint32_t r, uint32_t s)
-{
- uint32_t ret = 0x12345678;
-
- __asm volatile("mfc0 %0, $%1, %2; nop;" : "=r"(ret) : "i"(r), "i"(s));
- return ret;
-}
-
-#define MTC0(v, r, s) __asm volatile("mtc0 %0, $%1, %2; nop;" :: "r"(v), "i"(r), "i"(s))
-
-#define CP0_CORE_CTRL 12 /* select 2 */
- #define CC_SW_RST0 1 /* reset core 0 */
- #define CC_SW_RST1 2 /* reset core 1 */
- #define CC_RPC0 0x100 /* dedicated reset entry core 0 */
- #define CC_RPC1 0x200 /* -- || -- core 1 */
- #define CC_SLEEP0M 0x10000 /* mask sleep core 0 */
- #define CC_SLEEP1M 0x20000 /* mask sleep core 1 */
-
-/* cores status, 12 select 3 */
-#define CS_MIRQ0_P 0x00001 /* mailbox IRQ for 0 pending */
-#define CS_MIRQ1_P 0x00002 /* || core 1 */
-#define CS_IRQ0_P 0x00100 /* peripheral IRQ for core 0 */
-#define CS_IRQ1_P 0x00200 /* || core 1 */
-#define CS_SLEEP0 0x10000 /* core 0 sleeping */
-#define CS_SLEEP1 0x20000 /* core 1 sleeping */
-
-/* cores reset entry & IRQ masks - 12 select 4 */
-#define REIM_MIRQ0_M 0x00001 /* allow mailbox IRQ for core 0 */
-#define REIM_MIRQ1_M 0x00002 /* allow mailbox IRQ for core 1 */
-#define REIM_IRQ0_M 0x00100 /* allow peripheral IRQ for core 0 */
-#define REIM_IRQ1_M 0x00200 /* allow peripheral IRQ for core 1 */
-#define REIM_ENTRY_M 0xfffff000 /* reset exception entry if RPCn=1 */
-
-#define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */
-
-#define CP0_CORE0_MBOX _(20), 0
-#define CP0_CORE1_MBOX _(20), 1
-
-
/* power management */
#define JZ_CPCCR 0x10000000 /* Clock Control Register */
Index: src/sys/arch/mips/ingenic/ingenic_var.h
diff -u src/sys/arch/mips/ingenic/ingenic_var.h:1.5 src/sys/arch/mips/ingenic/ingenic_var.h:1.6
--- src/sys/arch/mips/ingenic/ingenic_var.h:1.5 Mon May 18 15:07:52 2015
+++ src/sys/arch/mips/ingenic/ingenic_var.h Sun May 21 06:49:13 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_var.h,v 1.5 2015/05/18 15:07:52 macallan Exp $ */
+/* $NetBSD: ingenic_var.h,v 1.6 2017/05/21 06:49:13 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -45,4 +45,14 @@ struct apbus_attach_args {
extern bus_space_tag_t ingenic_memt;
void apbus_init(void);
+uint32_t mips_cp0_corectrl_read(void);
+uint32_t mips_cp0_corestatus_read(void);
+uint32_t mips_cp0_corereim_read(void);
+uint32_t mips_cp0_corembox_read(u_int);
+
+void mips_cp0_corectrl_write(uint32_t);
+void mips_cp0_corestatus_write(uint32_t);
+void mips_cp0_corereim_write(uint32_t);
+void mips_cp0_corembox_write(u_int, uint32_t);
+
#endif /* INGENIC_VAR_H */
Added files:
Index: src/sys/arch/mips/ingenic/ingenic_coreregs.h
diff -u /dev/null src/sys/arch/mips/ingenic/ingenic_coreregs.h:1.1
--- /dev/null Sun May 21 06:49:13 2017
+++ src/sys/arch/mips/ingenic/ingenic_coreregs.h Sun May 21 06:49:13 2017
@@ -0,0 +1,70 @@
+/* $NetBSD: ingenic_coreregs.h,v 1.1 2017/05/21 06:49:13 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef INGENIC_COREREGS_H
+#define INGENIC_COREREGS_H
+
+#ifdef _LOCORE
+#define _(n) __CONCAT($,n)
+#else
+#define _(n) n
+#endif
+
+/* cores status, 12 select 3 */
+#define CP0_CORE_CTRL _(12), 2 /* select 2 */
+#define CC_SW_RST0 __BIT(0) /* reset core 0 */
+#define CC_SW_RST1 __BIT(1) /* reset core 1 */
+#define CC_RPC0 __BIT(8) /* dedicated reset entry core 0 */
+#define CC_RPC1 __BIT(9) /* -- || -- core 1 */
+#define CC_SLEEP0M __BIT(16) /* mask sleep core 0 */
+#define CC_SLEEP1M __BIT(17) /* mask sleep core 1 */
+
+/* cores status, 12 select 3 */
+#define CP0_CORE_STATUS _(12), 3
+#define CS_MIRQ0_P __BIT(0) /* mailbox IRQ for 0 pending */
+#define CS_MIRQ1_P __BIT(1) /* || core 1 */
+#define CS_IRQ0_P __BIT(8) /* peripheral IRQ for core 0 */
+#define CS_IRQ1_P __BIT(9) /* || core 1 */
+#define CS_SLEEP0 __BIT(16) /* core 0 sleeping */
+#define CS_SLEEP1 __BIT(17) /* core 1 sleeping */
+
+/* cores reset entry & IRQ masks - 12 select 4 */
+#define CP0_CORE_REIM _(12), 4
+#define REIM_MIRQ0_M __BIT(0) /* allow mailbox IRQ for core 0 */
+#define REIM_MIRQ1_M __BIT(1) /* allow mailbox IRQ for core 1 */
+#define REIM_IRQ0_M __BIT(8) /* allow peripheral IRQ for core 0 */
+#define REIM_IRQ1_M __BIT(9) /* allow peripheral IRQ for core 1 */
+#define REIM_ENTRY_M __BITS(31,16) /* reset exception entry if RPCn=1 */
+
+#define CP0_SPINLOCK _(12), 5
+#define CP0_SPINATOMIC _(12), 6
+
+#define CP0_CORE0_MBOX _(20), 0
+#define CP0_CORE1_MBOX _(20), 1
+
+#endif /* INGENIC_COREREGS_H */
Index: src/sys/arch/mips/mips/locore_ingenic.S
diff -u /dev/null src/sys/arch/mips/mips/locore_ingenic.S:1.1
--- /dev/null Sun May 21 06:49:13 2017
+++ src/sys/arch/mips/mips/locore_ingenic.S Sun May 21 06:49:13 2017
@@ -0,0 +1,150 @@
+/* $NetBSD: locore_ingenic.S,v 1.1 2017/05/21 06:49:13 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2017 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <mips/asm.h>
+RCSID("$NetBSD: locore_ingenic.S,v 1.1 2017/05/21 06:49:13 skrll Exp $")
+
+#include <mips/cpuregs.h>
+#include <mips/ingenic/ingenic_coreregs.h>
+
+#include "assym.h"
+
+ .set noreorder
+ .set noat
+ .set arch=mips32r2
+
+ .text
+
+/*
+ * uint32_t mips_cp0_corectrl_read(void)
+ *
+ * Return the current value of the CP0 Core Control register.
+ */
+LEAF(mips_cp0_corectrl_read)
+ mfc0 v0, CP0_CORE_CTRL
+ jr ra
+ nop
+END(mips_cp0_corectrl_read)
+
+/*
+ * void mips_cp0_corectrl_write(uint32_t)
+ *
+ * Set the value of the CP0 Core Control register.
+ */
+LEAF(mips_cp0_corectrl_write)
+ mtc0 a0, CP0_CORE_CTRL
+ jr.hb ra
+ nop
+END(mips_cp0_corectrl_write)
+
+/*
+ * uint32_t mips_cp0_corestatus_read(void)
+ *
+ * Return the current value of the CP0 Core Status register.
+ */
+LEAF(mips_cp0_corestatus_read)
+ mfc0 v0, CP0_CORE_STATUS
+ jr ra
+ nop
+END(mips_cp0_corestatus_read)
+
+/*
+ * void mips_cp0_corestatus_write(uint32_t)
+ *
+ * Set the value of the CP0 Core Status register.
+ */
+LEAF(mips_cp0_corestatus_write)
+ mtc0 a0, CP0_CORE_STATUS
+ jr.hb ra
+ nop
+END(mips_cp0_corestatus_write)
+
+
+/*
+ * uint32_t mips_cp0_corereim_read(void)
+ *
+ * Return the current value of the CP0 Reset Entry & IRQ Mask register.
+ */
+LEAF(mips_cp0_corereim_read)
+ mfc0 v0, CP0_CORE_REIM
+ jr ra
+ nop
+END(mips_cp0_corereim_read)
+
+/*
+ * void mips_cp0_corereim_write(uint32_t)
+ *
+ * Set the value of the CP0 Core Reset Entry & IRQ Mask register.
+ */
+LEAF(mips_cp0_corereim_write)
+ mtc0 a0, CP0_CORE_REIM
+ jr.hb ra
+ nop
+END(mips_cp0_corereim_write)
+
+
+/*
+ * uintptr_t mips_cp0_corembox_read(u_int sel)
+ *
+ * Return the current value of the selected CP0 Mailbox register.
+ */
+LEAF(mips_cp0_corembox_read)
+ sll a0, 2
+ PTR_LA t9, 1f
+ PTR_ADDU t9, a0
+ jr t9
+ nop
+1:
+ jr ra
+ mfc0 v0, CP0_CORE0_MBOX
+ jr ra
+ mfc0 v0, CP0_CORE1_MBOX
+ jr ra
+END(mips_cp0_corembox_read)
+
+/*
+ * void mips_cp0_watchlo_write(u_int sel, uinte32_t val)
+ *
+ * Set the current value of the selected CP0 Mailbox register.
+ */
+LEAF(mips_cp0_corembox_write)
+ sll a0, 2
+ PTR_LA t9, 1f
+ PTR_ADDU t9, a0
+ jr t9
+ nop
+1:
+ jr.hb ra
+ mtc0 a1, CP0_CORE0_MBOX
+ jr.hb ra
+ mtc0 a1, CP0_CORE1_MBOX
+ jr.hb ra
+END(mips_cp0_corembox_write)
