Module Name: src
Committed By: skrll
Date: Wed May 24 06:31:07 UTC 2017
Modified Files:
src/sys/arch/arm/arm32: pmap.c
Log Message:
Check the "Havard TLB" maintenance operations if the "Unified TLB"
maintenance opeations don't include invalidate by ASID. Some CPUs, e.g.
Cortex-A8, have Havard TLBs and report ASID operations this way.
To generate a diff of this commit:
cvs rdiff -u -r1.348 -r1.349 src/sys/arch/arm/arm32/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/pmap.c
diff -u src/sys/arch/arm/arm32/pmap.c:1.348 src/sys/arch/arm/arm32/pmap.c:1.349
--- src/sys/arch/arm/arm32/pmap.c:1.348 Wed May 24 06:27:33 2017
+++ src/sys/arch/arm/arm32/pmap.c Wed May 24 06:31:07 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.348 2017/05/24 06:27:33 skrll Exp $ */
+/* $NetBSD: pmap.c,v 1.349 2017/05/24 06:31:07 skrll Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@@ -217,7 +217,7 @@
#include <arm/locore.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.348 2017/05/24 06:27:33 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.349 2017/05/24 06:31:07 skrll Exp $");
//#define PMAP_DEBUG
#ifdef PMAP_DEBUG
@@ -7524,6 +7524,8 @@ pmap_pte_init_armv7(void)
*/
if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) {
arm_has_tlbiasid_p = true;
+ } else if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(12,15)) >= 2) {
+ arm_has_tlbiasid_p = true;
}
pte_l1_s_prot_u = L1_S_PROT_U_armv7;
