Module Name: src
Committed By: skrll
Date: Sat Jul 15 06:20:22 UTC 2017
Modified Files:
src/sys/arch/arm/arm: cpufunc_asm_armv6.S
Log Message:
Spell invalidate correctly in comments. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/arm/cpufunc_asm_armv6.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc_asm_armv6.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_armv6.S:1.7 src/sys/arch/arm/arm/cpufunc_asm_armv6.S:1.8
--- src/sys/arch/arm/arm/cpufunc_asm_armv6.S:1.7 Fri Aug 1 05:53:31 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_armv6.S Sat Jul 15 06:20:22 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_armv6.S,v 1.7 2014/08/01 05:53:31 skrll Exp $ */
+/* $NetBSD: cpufunc_asm_armv6.S,v 1.8 2017/07/15 06:20:22 skrll Exp $ */
/*
* Copyright (c) 2002, 2005 ARM Limited
@@ -100,7 +100,7 @@ END(armv6_dcache_wb_range)
ENTRY(armv6_dcache_wbinv_range)
add r1, r1, r0
sub r1, r1, #1
- mcrr p15, 0, r1, r0, c14 /* clean and invaliate D cache range */
+ mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_dcache_wbinv_range)
@@ -114,7 +114,7 @@ END(armv6_dcache_wbinv_range)
ENTRY(armv6_dcache_inv_range)
add r1, r1, r0
sub r1, r1, #1
- mcrr p15, 0, r1, r0, c6 /* invaliate D cache range */
+ mcrr p15, 0, r1, r0, c6 /* invalidate D cache range */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_dcache_inv_range)
@@ -123,8 +123,8 @@ END(armv6_dcache_inv_range)
ENTRY(armv6_idcache_wbinv_range)
add r1, r1, r0
sub r1, r1, #1
- mcrr p15, 0, r1, r0, c5 /* invaliate I cache range */
- mcrr p15, 0, r1, r0, c14 /* clean & invaliate D cache range */
+ mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */
+ mcrr p15, 0, r1, r0, c14 /* clean & invalidate D cache range */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv6_idcache_wbinv_range)
