Module Name: src
Committed By: maya
Date: Tue Aug 8 09:33:41 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
In working around loongson errata clear BTB and RAS, same as
other operating systems.
15 Errata: Issue of Out-of-order in loongson (translated)
In loongson 2F, because of the branch prediction, sometimes the CPU
may fetch the instructions from some unexpected area (for example I/O
space). It is an invalid operation. There are two ways for the CPU to
choose the branch target. The first one is predicting the branch
target according to the branch target history. The second one is
calculating the branch target by the ALU. There are most 8
instructions in the instruction window at the same time in loongson2f
(Remember the loongson 2f is superscalar, right?). Hence, the
branch target of an indirect branch(such as jr) could be got(may be
predicted by the branch target history) earlier and the instrctions of
the branch target could be prefetched even if there are branch
instructions before it. As a result, it is possible to fetch the
instructions from I/O region( say out-of the physical address range of
[0- 0x100000]) in kernel model because of the instruction prefetch of
the branch target.
There are some suggestions to prevent prefetching instructions from
the I/O region in kernel mode.
(1) When switching from user model to kernel model, you should flush
the branch target history such as BTB and RAS.
(2) Doing some tricks to the indirect branch target to make sure that
the indirect branch target can not be in the I/O region.
To generate a diff of this commit:
cvs rdiff -u -r1.100 -r1.101 src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.100 src/sys/arch/mips/mips/mipsX_subr.S:1.101
--- src/sys/arch/mips/mips/mipsX_subr.S:1.100 Mon May 15 10:59:24 2017
+++ src/sys/arch/mips/mips/mipsX_subr.S Tue Aug 8 09:33:41 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.100 2017/05/15 10:59:24 skrll Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.101 2017/08/08 09:33:41 maya Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -1289,7 +1289,7 @@ NESTED_NOPROFILE(MIPSX(user_reserved_ins
* Save a minimum of registers to see if this is rdhwr $3,$29
*/
#ifdef MIPS3_LOONGSON2
- li k0, MIPS_DIAG_BTB_CLEAR
+ li k0, MIPS_DIAG_BTB_CLEAR | MIPS_DIAG_RAS_DISABLE
mtc0 k0, MIPS_COP_0_DIAG
#endif
/* K1 already has CURLWP */
@@ -1354,7 +1354,7 @@ NESTED_NOPROFILE(MIPSX(user_gen_exceptio
* Save all the registers except the kernel temporaries onto the stack.
*/
#ifdef MIPS3_LOONGSON2
- li k0, MIPS_DIAG_BTB_CLEAR
+ li k0, MIPS_DIAG_BTB_CLEAR | MIPS_DIAG_RAS_DISABLE
mtc0 k0, MIPS_COP_0_DIAG
#endif
/* K1 already has CURLWP */
@@ -1469,7 +1469,7 @@ NESTED_NOPROFILE(MIPSX(user_intr), CALLF
* We don't need to save s0 - s8 because the compiler does it for us.
*/
#ifdef MIPS3_LOONGSON2
- li k0, MIPS_DIAG_BTB_CLEAR
+ li k0, MIPS_DIAG_BTB_CLEAR | MIPS_DIAG_RAS_DISABLE
mtc0 k0, MIPS_COP_0_DIAG
#endif
/* k1 contains curlwp */
@@ -1661,7 +1661,7 @@ NESTED_NOPROFILE(MIPSX(systemcall), CALL
* Save all the registers but kernel temporaries onto the stack.
*/
#ifdef MIPS3_LOONGSON2
- li k0, MIPS_DIAG_BTB_CLEAR
+ li k0, MIPS_DIAG_BTB_CLEAR | MIPS_DIAG_RAS_DISABLE
mtc0 k0, MIPS_COP_0_DIAG
#endif
/* k1 already contains cpulwp */
@@ -2656,7 +2656,7 @@ MIPSX(user_return):
REG_L s7, CALLFRAME_SIZ+TF_REG_S7(sp) # $23
REG_L s8, CALLFRAME_SIZ+TF_REG_S8(sp) # $30
#ifdef MIPS3_LOONGSON2
- li t0, (MIPS_DIAG_BTB_CLEAR|MIPS_DIAG_ITLB_CLEAR)
+ li t0, (MIPS_DIAG_ITLB_CLEAR | MIPS_DIAG_BTB_CLEAR | MIPS_DIAG_RAS_DISABLE)
mtc0 t0, MIPS_COP_0_DIAG
#endif
MIPSX(user_intr_return):
