Module Name: src
Committed By: nisimura
Date: Tue Aug 22 18:35:09 UTC 2017
Modified Files:
src/sys/arch/aarch64/aarch64: vectors.S
Log Message:
use lr for current x30. some comment snip
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/aarch64/vectors.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/vectors.S
diff -u src/sys/arch/aarch64/aarch64/vectors.S:1.2 src/sys/arch/aarch64/aarch64/vectors.S:1.3
--- src/sys/arch/aarch64/aarch64/vectors.S:1.2 Tue Aug 22 17:08:03 2017
+++ src/sys/arch/aarch64/aarch64/vectors.S Tue Aug 22 18:35:09 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: vectors.S,v 1.2 2017/08/22 17:08:03 nisimura Exp $ */
+/* $NetBSD: vectors.S,v 1.3 2017/08/22 18:35:09 nisimura Exp $ */
#include <aarch64/asm.h>
#include "assym.h"
@@ -96,7 +96,7 @@ lr .req x30 /* link register */
.p2align 11
ENTRY(el1_vectors)
/*
- * Exception taken from current Exception Level with SP_EL1.
+ * A64 exception taken from current Exception Level with SP_EL1.
* (These shouldn't happen)
*/
VECT_INVAL 1, BAD_SYNC /* Synchronous EL1t */
@@ -104,24 +104,24 @@ ENTRY(el1_vectors)
VECT_INVAL 1, BAD_FIQ /* FIQ EL1t */
VECT_INVAL 1, BAD_ERROR /* Error EL1t */
/*
- * Exception taken from current Exception Level with SP.
- * There are entries for exceptions caused in EL1 (kernel exceptions).
+ * A64 exception taken from current Exception Level with SP.
+ * EL1 (kernel exceptions)
*/
VECT_ENTRY el1_sync /* Synchronous EL1h */
VECT_ENTRY el1_irq /* IRQ EL1h */
VECT_INVAL 1, BAD_FIQ /* FIQ EL1h */
VECT_INVAL 1, BAD_ERROR /* Error EL1h */
/*
- * Exception taken from lower Exception Level which is using AArch64
- * There are entries for exceptions caused in EL0 (native user exceptions).
+ * A64 exception taken from lower Exception Level.
+ * EL0 (native user exceptions)
*/
VECT_ENTRY el0_sync /* Synchronous 64bit EL0 */
VECT_ENTRY el0_irq /* IRQ 64bit EL0 */
VECT_INVAL 0, BAD_FIQ /* FIQ 64bit EL0 */
VECT_INVAL 0, BAD_ERROR /* Error 64bit EL0 */
/*
- * Exception taken from lower Exception Level which is using AArch32
- * There are entries for exceptions caused in EL0 (compat user exceptions).
+ * A32 exception taken from lower Exception Level.
+ * EL0 (compat user exceptions)
*/
VECT_ENTRY el0_32sync /* Synchronous 32bit EL0 */
VECT_ENTRY el0_32irq /* IRQ 32bit EL0 */
@@ -130,7 +130,7 @@ ENTRY(el1_vectors)
ENTRY(el1_sync)
exception_entry 1
- adr x30, exception_trap_exit
+ adr lr, exception_trap_exit
mov x0, sp
mov x1, xzr
b trap
@@ -138,14 +138,14 @@ END(el1_sync)
ENTRY(el1_irq)
exception_entry 1
- adr x30, exception_trap_exit
+ adr lr, exception_trap_exit
mov x0, sp
b interrupt
END(el1_irq)
ENTRY(el0_sync)
exception_entry 0
- adr x30, exception_trap_exit
+ adr lr, exception_trap_exit
mov x0, sp
mov x1, xzr
b trap
@@ -153,14 +153,14 @@ END(el0_sync)
ENTRY(el0_irq)
exception_entry 0
- adr x30, exception_trap_exit
+ adr lr, exception_trap_exit
mov x0, sp
b interrupt
END(el0_irq)
ENTRY(el0_32sync)
exception_entry 0, 32
- adr x30, exception_trap_exit
+ adr lr, exception_trap_exit
mov x0, sp
mov x1, xzr
b trap
@@ -168,7 +168,7 @@ END(el0_32sync)
ENTRY(el0_32irq)
exception_entry 0, 32
- adr x30, exception_trap_exit
+ adr lr, exception_trap_exit
mov x0, sp
b interrupt
END(el0_32irq)
