Module Name: src
Committed By: kre
Date: Tue Aug 22 21:23:58 UTC 2017
Modified Files:
src/sys/arch/shark/shark: sequoia.h
Log Message:
Add () around "1 << n' in #define's, without it ~NAME is "~1 << n" which is
not what is wanted at all (and which caused the << of a negative number issue.)
Making the values unsigned is harmless (perhaps even better) so those that
were changed are still that way.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/shark/shark/sequoia.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/shark/shark/sequoia.h
diff -u src/sys/arch/shark/shark/sequoia.h:1.3 src/sys/arch/shark/shark/sequoia.h:1.4
--- src/sys/arch/shark/shark/sequoia.h:1.3 Tue Aug 22 12:52:24 2017
+++ src/sys/arch/shark/shark/sequoia.h Tue Aug 22 21:23:58 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: sequoia.h,v 1.3 2017/08/22 12:52:24 joerg Exp $ */
+/* $NetBSD: sequoia.h,v 1.4 2017/08/22 21:23:58 kre Exp $ */
/*
* Copyright 1997
@@ -109,39 +109,39 @@
#define PMC_CCR_REG 0x000
#define PMC_CCR_INIT 0x000
#define CCR_V_CNCLKSEL 0
-#define CCR_M_CNCLKSEL 0x7 << CCR_V_CNCLKSEL
+#define CCR_M_CNCLKSEL (0x7 << CCR_V_CNCLKSEL)
#define CCR_V_CNCLKSEL0 0
-#define CCR_M_CNCLKSEL0 1 << CCR_V_CNCLKSEL0
+#define CCR_M_CNCLKSEL0 (1 << CCR_V_CNCLKSEL0)
#define CCR_V_CNCLKSEL1 1
-#define CCR_M_CNCLKSEL1 1 << CCR_V_CNCLKSEL1
+#define CCR_M_CNCLKSEL1 (1 << CCR_V_CNCLKSEL1)
#define CCR_V_CNCLKSEL2 2
-#define CCR_M_CNCLKSEL2 1 << CCR_V_CNCLKSEL2
+#define CCR_M_CNCLKSEL2 (1 << CCR_V_CNCLKSEL2)
#define CCR_V_CNSRVEN 3
-#define CCR_M_CNSRVEN 1 << CCR_V_CNSRVEN
+#define CCR_M_CNSRVEN (1 << CCR_V_CNSRVEN)
#define CCR_V_SLCLKSEL 4
-#define CCR_M_SLCLKSEL 0x7 << CCR_V_SLCLKSEL
+#define CCR_M_SLCLKSEL (0x7 << CCR_V_SLCLKSEL)
#define CCR_V_SLCLKSEL0 4
-#define CCR_M_SLCLKSEL0 1 << CCR_V_SLCLKSEL0
+#define CCR_M_SLCLKSEL0 (1 << CCR_V_SLCLKSEL0)
#define CCR_V_SLCLKSEL1 5
-#define CCR_M_SLCLKSEL1 1 << CCR_V_SLCLKSEL1
+#define CCR_M_SLCLKSEL1 (1 << CCR_V_SLCLKSEL1)
#define CCR_V_SLCLKSEL2 6
-#define CCR_M_SLCLKSEL2 1 << CCR_V_SLCLKSEL2
+#define CCR_M_SLCLKSEL2 (1 << CCR_V_SLCLKSEL2)
#define CCR_V_SLWCLKEN 7
-#define CCR_M_SLWCLKEN 1 << CCR_V_SLWCLKEN
+#define CCR_M_SLWCLKEN (1 << CCR_V_SLWCLKEN)
#define CCR_V_SLPSLWEN 8
-#define CCR_M_SLPSLWEN 1 << CCR_V_SLPSLWEN
+#define CCR_M_SLPSLWEN (1 << CCR_V_SLPSLWEN)
#define CCR_V_DZSLWEN 9
-#define CCR_M_DZSLWEN 1 << CCR_V_DZSLWEN
+#define CCR_M_DZSLWEN (1 << CCR_V_DZSLWEN)
#define CCR_V_SPNDSLWEN 10
-#define CCR_M_SPNDSLWEN 1 << CCR_V_SPNDSLWEN
+#define CCR_M_SPNDSLWEN (1 << CCR_V_SPNDSLWEN)
#define CCR_V_LBSLWEN 11
-#define CCR_M_LBSLWEN 1 << CCR_V_LBSLWEN
+#define CCR_M_LBSLWEN (1 << CCR_V_LBSLWEN)
#define CCR_V_DZONHALT 12
-#define CCR_M_DZONHALT 1 << CCR_V_DZONHALT
+#define CCR_M_DZONHALT (1 << CCR_V_DZONHALT)
#define CCR_V_LBST 14
-#define CCR_M_LBST 1 << CCR_V_LBST
+#define CCR_M_LBST (1 << CCR_V_LBST)
#define CCR_V_VLBST 15
-#define CCR_M_VLBST 1 << CCR_V_VLBST
+#define CCR_M_VLBST (1 << CCR_V_VLBST)
/*
** Conserve Clock Selects
@@ -193,41 +193,41 @@
#define PMC_PMSR_REG 0x001
#define PMC_PMSR_INIT ( PMSR_M_WAKESRC | PMSR_M_PMISRC | PMMD_ON )
#define PMSR_V_WAKESRC 0
-#define PMSR_M_WAKESRC 0x7 << PMSR_V_WAKESRC
+#define PMSR_M_WAKESRC (0x7 << PMSR_V_WAKESRC)
#define PMSR_V_WAKESRC0 0
-#define PMSR_M_WAKESRC0 1 << PMSR_V_WAKESRC0
+#define PMSR_M_WAKESRC0 (1 << PMSR_V_WAKESRC0)
#define PMSR_V_WAKESRC1 1
-#define PMSR_M_WAKESRC1 1 << PMSR_V_WAKESRC1
+#define PMSR_M_WAKESRC1 (1 << PMSR_V_WAKESRC1)
#define PMSR_V_WAKESRC2 2
-#define PMSR_M_WAKESRC2 1 << PMSR_V_WAKESRC2
+#define PMSR_M_WAKESRC2 (1 << PMSR_V_WAKESRC2)
#define PMSR_V_ACPWR 3
-#define PMSR_M_ACPWR 1 << PMSR_V_ACPWR
+#define PMSR_M_ACPWR (1 << PMSR_V_ACPWR)
#define PMSR_V_PMISRC 4
-#define PMSR_M_PMISRC 0x1F << PMSR_V_PMISRC
+#define PMSR_M_PMISRC (0x1F << PMSR_V_PMISRC)
#define PMSR_V_PMISRC0 4
-#define PMSR_M_PMISRC0 1 << PMSR_V_PMISRC0
+#define PMSR_M_PMISRC0 (1 << PMSR_V_PMISRC0)
#define PMSR_V_PMISRC1 5
-#define PMSR_M_PMISRC1 1 << PMSR_V_PMISRC1
+#define PMSR_M_PMISRC1 (1 << PMSR_V_PMISRC1)
#define PMSR_V_PMISRC2 6
-#define PMSR_M_PMISRC2 1 << PMSR_V_PMISRC2
+#define PMSR_M_PMISRC2 (1 << PMSR_V_PMISRC2)
#define PMSR_V_PMISRC3 7
-#define PMSR_M_PMISRC3 1 << PMSR_V_PMISRC3
+#define PMSR_M_PMISRC3 (1 << PMSR_V_PMISRC3)
#define PMSR_V_PMISRC4 8
-#define PMSR_M_PMISRC4 1 << PMSR_V_PMISRC4
+#define PMSR_M_PMISRC4 (1 << PMSR_V_PMISRC4)
#define PMSR_V_RESUME 9
-#define PMSR_M_RESUME 1 << PMSR_V_RESUME
+#define PMSR_M_RESUME (1 << PMSR_V_RESUME)
#define PMSR_V_WAKE0STATUS 10
-#define PMSR_M_WAKE0STATUS 1 << PMSR_V_WAKE0STATUS
+#define PMSR_M_WAKE0STATUS (1 << PMSR_V_WAKE0STATUS)
#define PMSR_V_WAKE1STATUS 11
-#define PMSR_M_WAKE1STATUS 1 << PMSR_V_WAKE1STATUS
+#define PMSR_M_WAKE1STATUS (1 << PMSR_V_WAKE1STATUS)
#define PMSR_V_PMMD 13
-#define PMSR_M_PMMD 0x7 << PMSR_V_PMMD
+#define PMSR_M_PMMD (0x7 << PMSR_V_PMMD)
#define PMSR_V_PMMD0 13
-#define PMSR_M_PMMD0 1 << PMSR_V_PMMD0
+#define PMSR_M_PMMD0 (1 << PMSR_V_PMMD0)
#define PMSR_V_PMMD1 14
-#define PMSR_M_PMMD1 1 << PMSR_V_PMMD1
+#define PMSR_M_PMMD1 (1 << PMSR_V_PMMD1)
#define PMSR_V_PMMD2 15
-#define PMSR_M_PMMD2 1 << PMSR_V_PMMD2
+#define PMSR_M_PMMD2 (1 << PMSR_V_PMMD2)
/*
** Wake-up Source
@@ -300,33 +300,33 @@
#define PMC_ASR_REG 0x002
#define PMC_ASR_INIT 0x0000
#define ASR_V_VIDACTV 0
-#define ASR_M_VIDACTV 1 << ASR_V_VIDACTV
+#define ASR_M_VIDACTV (1 << ASR_V_VIDACTV)
#define ASR_V_HDACTV 1
-#define ASR_M_HDACTV 1 << ASR_V_HDACTV
+#define ASR_M_HDACTV (1 << ASR_V_HDACTV)
#define ASR_V_FLPACTV 2
-#define ASR_M_FLPACTV 1 << ASR_V_FLPACTV
+#define ASR_M_FLPACTV (1 << ASR_V_FLPACTV)
#define ASR_V_KBDACTV 3
-#define ASR_M_KBDACTV 1 << ASR_V_KBDACTV
+#define ASR_M_KBDACTV (1 << ASR_V_KBDACTV)
#define ASR_V_SIOACTV 4
-#define ASR_M_SIOACTV 1 << ASR_V_SIOACTV
+#define ASR_M_SIOACTV (1 << ASR_V_SIOACTV)
#define ASR_V_PIOACTV 5
-#define ASR_M_PIOACTV 1 << ASR_V_PIOACTV
+#define ASR_M_PIOACTV (1 << ASR_V_PIOACTV)
#define ASR_V_PROG0ACTV 6
-#define ASR_M_PROG0ACTV 1 << ASR_V_PROG0ACTV
+#define ASR_M_PROG0ACTV (1 << ASR_V_PROG0ACTV)
#define ASR_V_PROG1ACTV 7
-#define ASR_M_PROG1ACTV 1 << ASR_V_PROG1ACTV
+#define ASR_M_PROG1ACTV (1 << ASR_V_PROG1ACTV)
#define ASR_V_PROG2ACTV 8
-#define ASR_M_PROG2ACTV 1 << ASR_V_PROG2ACTV
+#define ASR_M_PROG2ACTV (1 << ASR_V_PROG2ACTV)
#define ASR_V_PROG3ACTV 9
-#define ASR_M_PROG3ACTV 1 << ASR_V_PROG3ACTV
+#define ASR_M_PROG3ACTV (1 << ASR_V_PROG3ACTV)
#define ASR_V_EXT0ACTV 12
-#define ASR_M_EXT0ACTV 1 << ASR_V_EXT0ACTV
+#define ASR_M_EXT0ACTV (1 << ASR_V_EXT0ACTV)
#define ASR_V_EXT1ACTV 13
-#define ASR_M_EXT1ACTV 1 << ASR_V_EXT1ACTV
+#define ASR_M_EXT1ACTV (1 << ASR_V_EXT1ACTV)
#define ASR_V_EXT2ACTV 14
-#define ASR_M_EXT2ACTV 1 << ASR_V_EXT2ACTV
+#define ASR_M_EXT2ACTV (1 << ASR_V_EXT2ACTV)
#define ASR_V_EXT3ACTV 15
-#define ASR_M_EXT3ACTV 1 << ASR_V_EXT3ACTV
+#define ASR_M_EXT3ACTV (1 << ASR_V_EXT3ACTV)
/*
**
@@ -354,33 +354,33 @@
#define PMC_PAMR_REG 0x003
#define PMC_PAMR_INIT 0x0000
#define PAMR_V_PAMSKVID 0
-#define PAMR_M_PAMSKVID 1 << PAMR_V_PAMSKVID
+#define PAMR_M_PAMSKVID (1 << PAMR_V_PAMSKVID)
#define PAMR_V_PAMSKHD 1
-#define PAMR_M_PAMSKHD 1 << PAMR_V_PAMSKHD
+#define PAMR_M_PAMSKHD (1 << PAMR_V_PAMSKHD)
#define PAMR_V_PAMSKFLP 2
-#define PAMR_M_PAMSKFLP 1 << PAMR_V_PAMSKFLP
+#define PAMR_M_PAMSKFLP (1 << PAMR_V_PAMSKFLP)
#define PAMR_V_PAMSKKDB 3
-#define PAMR_M_PAMSKKDB 1 << PAMR_V_PAMSKKDB
+#define PAMR_M_PAMSKKDB (1 << PAMR_V_PAMSKKDB)
#define PAMR_V_PAMSKSIO 4
-#define PAMR_M_PAMSKSIO 1 << PAMR_V_PAMSKSIO
+#define PAMR_M_PAMSKSIO (1 << PAMR_V_PAMSKSIO)
#define PAMR_V_PAMSKPIO 5
-#define PAMR_M_PAMSKPIO 1 << PAMR_V_PAMSKPIO
+#define PAMR_M_PAMSKPIO (1 << PAMR_V_PAMSKPIO)
#define PAMR_V_PAMSKPROG0 6
-#define PAMR_M_PAMSKPROG0 1 << PAMR_V_PAMSKPROG0
+#define PAMR_M_PAMSKPROG0 (1 << PAMR_V_PAMSKPROG0)
#define PAMR_V_PAMSKPROG1 7
-#define PAMR_M_PAMSKPROG1 1 << PAMR_V_PAMSKPROG1
+#define PAMR_M_PAMSKPROG1 (1 << PAMR_V_PAMSKPROG1)
#define PAMR_V_PAMSKPROG2 8
-#define PAMR_M_PAMSKPROG2 1 << PAMR_V_PAMSKPROG2
+#define PAMR_M_PAMSKPROG2 (1 << PAMR_V_PAMSKPROG2)
#define PAMR_V_PAMSKPROG3 9
-#define PAMR_M_PAMSKPROG3 1 << PAMR_V_PAMSKPROG3
+#define PAMR_M_PAMSKPROG3 (1 << PAMR_V_PAMSKPROG3)
#define PAMR_V_PAMSKEACT0 12
-#define PAMR_M_PAMSKEACT0 1 << PAMR_V_PAMSKEACT0
+#define PAMR_M_PAMSKEACT0 (1 << PAMR_V_PAMSKEACT0)
#define PAMR_V_PAMSKEACT1 13
-#define PAMR_M_PAMSKEACT1 1 << PAMR_V_PAMSKEACT1
+#define PAMR_M_PAMSKEACT1 (1 << PAMR_V_PAMSKEACT1)
#define PAMR_V_PAMSKEACT2 14
-#define PAMR_M_PAMSKEACT2 1 << PAMR_V_PAMSKEACT2
+#define PAMR_M_PAMSKEACT2 (1 << PAMR_V_PAMSKEACT2)
#define PAMR_V_PAMSKEACT3 15
-#define PAMR_M_PAMSKEACT3 1 << PAMR_V_PAMSKEACT3
+#define PAMR_M_PAMSKEACT3 (1 << PAMR_V_PAMSKEACT3)
/*
**
@@ -414,33 +414,33 @@
PMIMR_M_IMSKEACT0 | PMIMR_M_IMSKEACT1 | \
PMIMR_M_IMSKEACT2 | PMIMR_M_IMSKEACT3 )
#define PMIMR_V_IMSKVID 0
-#define PMIMR_M_IMSKVID 1 << PMIMR_V_IMSKVID
+#define PMIMR_M_IMSKVID (1 << PMIMR_V_IMSKVID)
#define PMIMR_V_IMSKHD 1
-#define PMIMR_M_IMSKHD 1 << PMIMR_V_IMSKHD
+#define PMIMR_M_IMSKHD (1 << PMIMR_V_IMSKHD)
#define PMIMR_V_IMSKFLP 2
-#define PMIMR_M_IMSKFLP 1 << PMIMR_V_IMSKFLP
+#define PMIMR_M_IMSKFLP (1 << PMIMR_V_IMSKFLP)
#define PMIMR_V_IMSKKDB 3
-#define PMIMR_M_IMSKKDB 1 << PMIMR_V_IMSKKDB
+#define PMIMR_M_IMSKKDB (1 << PMIMR_V_IMSKKDB)
#define PMIMR_V_IMSKSIO 4
-#define PMIMR_M_IMSKSIO 1 << PMIMR_V_IMSKSIO
+#define PMIMR_M_IMSKSIO (1 << PMIMR_V_IMSKSIO)
#define PMIMR_V_IMSKPIO 5
-#define PMIMR_M_IMSKPIO 1 << PMIMR_V_IMSKPIO
+#define PMIMR_M_IMSKPIO (1 << PMIMR_V_IMSKPIO)
#define PMIMR_V_IMSKPROG0 6
-#define PMIMR_M_IMSKPROG0 1 << PMIMR_V_IMSKPROG0
+#define PMIMR_M_IMSKPROG0 (1 << PMIMR_V_IMSKPROG0)
#define PMIMR_V_IMSKPROG1 7
-#define PMIMR_M_IMSKPROG1 1 << PMIMR_V_IMSKPROG1
+#define PMIMR_M_IMSKPROG1 (1 << PMIMR_V_IMSKPROG1)
#define PMIMR_V_IMSKPROG2 8
-#define PMIMR_M_IMSKPROG2 1 << PMIMR_V_IMSKPROG2
+#define PMIMR_M_IMSKPROG2 (1 << PMIMR_V_IMSKPROG2)
#define PMIMR_V_IMSKPROG3 9
-#define PMIMR_M_IMSKPROG3 1 << PMIMR_V_IMSKPROG3
+#define PMIMR_M_IMSKPROG3 (1 << PMIMR_V_IMSKPROG3)
#define PMIMR_V_IMSKEACT0 12
-#define PMIMR_M_IMSKEACT0 1 << PMIMR_V_IMSKEACT0
+#define PMIMR_M_IMSKEACT0 (1 << PMIMR_V_IMSKEACT0)
#define PMIMR_V_IMSKEACT1 13
-#define PMIMR_M_IMSKEACT1 1 << PMIMR_V_IMSKEACT1
+#define PMIMR_M_IMSKEACT1 (1 << PMIMR_V_IMSKEACT1)
#define PMIMR_V_IMSKEACT2 14
-#define PMIMR_M_IMSKEACT2 1 << PMIMR_V_IMSKEACT2
+#define PMIMR_M_IMSKEACT2 (1 << PMIMR_V_IMSKEACT2)
#define PMIMR_V_IMSKEACT3 15
-#define PMIMR_M_IMSKEACT3 1 << PMIMR_V_IMSKEACT3
+#define PMIMR_M_IMSKEACT3 (1 << PMIMR_V_IMSKEACT3)
/*
**
@@ -464,29 +464,29 @@
#define PMC_HRCR_REG 0x005
#define PMC_HRCR_INIT 0x0000
#define HRCR_V_HTRGDLY 0
-#define HRCR_M_HTRGDLY 0x7 << HRCR_V_HTRGDLY
+#define HRCR_M_HTRGDLY (0x7 << HRCR_V_HTRGDLY)
#define HRCR_V_HTRGDLY0 0
-#define HRCR_M_HTRGDLY0 1 << HRCR_V_HTRGDLY0
+#define HRCR_M_HTRGDLY0 (1 << HRCR_V_HTRGDLY0)
#define HRCR_V_HTRGDLY1 1
-#define HRCR_M_HTRGDLY1 1 << HRCR_V_HTRGDLY1
+#define HRCR_M_HTRGDLY1 (1 << HRCR_V_HTRGDLY1)
#define HRCR_V_HTRGDLY2 2
-#define HRCR_M_HTRGDLY2 1 << HRCR_V_HTRGDLY2
+#define HRCR_M_HTRGDLY2 (1 << HRCR_V_HTRGDLY2)
#define HRCR_V_HTRGRAT 3
-#define HRCR_M_HTRGRAT 0x7 << HRCR_V_HTRGRAT
+#define HRCR_M_HTRGRAT (0x7 << HRCR_V_HTRGRAT)
#define HRCR_V_HTRGRAT0 3
-#define HRCR_M_HTRGRAT0 1 << HRCR_V_HTRGRAT0
+#define HRCR_M_HTRGRAT0 (1 << HRCR_V_HTRGRAT0)
#define HRCR_V_HTRGRAT1 4
-#define HRCR_M_HTRGRAT1 1 << HRCR_V_HTRGRAT1
+#define HRCR_M_HTRGRAT1 (1 << HRCR_V_HTRGRAT1)
#define HRCR_V_HTRGRAT2 5
-#define HRCR_M_HTRGRAT2 1 << HRCR_V_HTRGRAT2
+#define HRCR_M_HTRGRAT2 (1 << HRCR_V_HTRGRAT2)
#define HRCR_V_HTRGEN 6
-#define HRCR_M_HTRGEN 1 << HRCR_V_HTRGEN
+#define HRCR_M_HTRGEN (1 << HRCR_V_HTRGEN)
#define HRCR_V_HTRGLOCK 7
-#define HRCR_M_HTRGLOCK 1 << HRCR_V_HTRGLOCK
+#define HRCR_M_HTRGLOCK (1 << HRCR_V_HTRGLOCK)
#define HRCR_V_FRCSLWEN 14
-#define HRCR_M_FRCSLWEN 1 << HRCR_V_FRCSLWEN
+#define HRCR_M_FRCSLWEN (1 << HRCR_V_FRCSLWEN)
#define HRCR_V_FRCSLWLOCK 15
-#define HRCR_M_FRCSLWLOCK 1 << HRCR_V_FRCSLWLOCK
+#define HRCR_M_FRCSLWLOCK (1 << HRCR_V_FRCSLWLOCK)
/*
** Heater Regulator Delay
@@ -537,31 +537,31 @@
PMIMCR_M_IMSKACPWR | PMIMCR_M_IMSKPROGTO | \
PMIMCR_M_IMSKGPTMR )
#define PMIMCR_V_IMSKSQ2PMI 0
-#define PMIMCR_M_IMSKSQ2PMI 1 << PMIMCR_V_IMSKSQ2PMI
+#define PMIMCR_M_IMSKSQ2PMI (1 << PMIMCR_V_IMSKSQ2PMI)
#define PMIMCR_V_IMSKLB 1
-#define PMIMCR_M_IMSKLB 1 << PMIMCR_V_IMSKLB
+#define PMIMCR_M_IMSKLB (1 << PMIMCR_V_IMSKLB)
#define PMIMCR_V_IMSKSPNDTO 2
-#define PMIMCR_M_IMSKSPNDTO 1 << PMIMCR_V_IMSKSPNDTO
+#define PMIMCR_M_IMSKSPNDTO (1 << PMIMCR_V_IMSKSPNDTO)
#define PMIMCR_V_IMSKSLPTO 3
-#define PMIMCR_M_IMSKSLPTO 1 << PMIMCR_V_IMSKSLPTO
+#define PMIMCR_M_IMSKSLPTO (1 << PMIMCR_V_IMSKSLPTO)
#define PMIMCR_V_IMSKDZTO 4
-#define PMIMCR_M_IMSKDZTO 1 << PMIMCR_V_IMSKDZTO
+#define PMIMCR_M_IMSKDZTO (1 << PMIMCR_V_IMSKDZTO)
#define PMIMCR_V_IMSKGENTO 5
-#define PMIMCR_M_IMSKGENTO 1 << PMIMCR_V_IMSKGENTO
+#define PMIMCR_M_IMSKGENTO (1 << PMIMCR_V_IMSKGENTO)
#define PMIMCR_V_IMSKACTV 6
-#define PMIMCR_M_IMSKACTV 1 << PMIMCR_V_IMSKACTV
+#define PMIMCR_M_IMSKACTV (1 << PMIMCR_V_IMSKACTV)
#define PMIMCR_V_IMSKPACTV 7
-#define PMIMCR_M_IMSKPACTV 1 << PMIMCR_V_IMSKPACTV
+#define PMIMCR_M_IMSKPACTV (1 << PMIMCR_V_IMSKPACTV)
#define PMIMCR_V_IMSKSACTV 8
-#define PMIMCR_M_IMSKSACTV 1 << PMIMCR_V_IMSKSACTV
+#define PMIMCR_M_IMSKSACTV (1 << PMIMCR_V_IMSKSACTV)
#define PMIMCR_V_IMSKSWSTBY 10
-#define PMIMCR_M_IMSKSWSTBY 1 << PMIMCR_V_IMSKSWSTBY
+#define PMIMCR_M_IMSKSWSTBY (1 << PMIMCR_V_IMSKSWSTBY)
#define PMIMCR_V_IMSKACPWR 11
-#define PMIMCR_M_IMSKACPWR 1 << PMIMCR_V_IMSKACPWR
+#define PMIMCR_M_IMSKACPWR (1 << PMIMCR_V_IMSKACPWR)
#define PMIMCR_V_IMSKPROGTO 12
-#define PMIMCR_M_IMSKPROGTO 1 << PMIMCR_V_IMSKPROGTO
+#define PMIMCR_M_IMSKPROGTO (1 << PMIMCR_V_IMSKPROGTO)
#define PMIMCR_V_IMSKGPTMR 13
-#define PMIMCR_M_IMSKGPTMR 1 << PMIMCR_V_IMSKGPTMR
+#define PMIMCR_M_IMSKGPTMR (1 << PMIMCR_V_IMSKGPTMR)
/*
**
@@ -591,41 +591,41 @@
#define PMC_GPCR_INIT ( REFRPRD_STOPPED | GPCR_M_GPIODIR0 | \
GPCR_M_GPIODIR1 )
#define GPCR_V_ACDISCNSRV 0
-#define GPCR_M_ACDISCNSRV 1 << GPCR_V_ACDISCNSRV
+#define GPCR_M_ACDISCNSRV (1 << GPCR_V_ACDISCNSRV)
#define GPCR_V_ACON 1
-#define GPCR_M_ACON 1 << GPCR_V_ACON
+#define GPCR_M_ACON (1 << GPCR_V_ACON)
#define GPCR_V_REFRPRD 2
-#define GPCR_M_REFRPRD 0x7 << GPCR_V_REFRPRD
+#define GPCR_M_REFRPRD (0x7 << GPCR_V_REFRPRD)
#define GPCR_V_REFRPRD0 2
-#define GPCR_M_REFRPRD0 1 << GPCR_V_REFRPRD0
+#define GPCR_M_REFRPRD0 (1 << GPCR_V_REFRPRD0)
#define GPCR_V_REFRPRD1 3
-#define GPCR_M_REFRPRD1 1 << GPCR_V_REFRPRD1
+#define GPCR_M_REFRPRD1 (1 << GPCR_V_REFRPRD1)
#define GPCR_V_REFRPRD2 4
-#define GPCR_M_REFRPRD2 1 << GPCR_V_REFRPRD2
+#define GPCR_M_REFRPRD2 (1 << GPCR_V_REFRPRD2)
#define GPCR_V_SLFREFEN 5
-#define GPCR_M_SLFREFEN 1 << GPCR_V_SLFREFEN
+#define GPCR_M_SLFREFEN (1 << GPCR_V_SLFREFEN)
#define GPCR_V_RINGS 6
-#define GPCR_M_RINGS 0x3 << GPCR_V_RINGS
+#define GPCR_M_RINGS (0x3 << GPCR_V_RINGS)
#define GPCR_V_GPIODATA 8
-#define GPCR_M_GPIODATA 0xF << GPCR_V_GPIODATA
+#define GPCR_M_GPIODATA (0xF << GPCR_V_GPIODATA)
#define GPCR_V_GPIODATA0 8
-#define GPCR_M_GPIODATA0 1 << GPCR_V_GPIODATA0
+#define GPCR_M_GPIODATA0 (1 << GPCR_V_GPIODATA0)
#define GPCR_V_GPIODATA1 9
-#define GPCR_M_GPIODATA1 1 << GPCR_V_GPIODATA1
+#define GPCR_M_GPIODATA1 (1 << GPCR_V_GPIODATA1)
#define GPCR_V_GPIODATA2 10
-#define GPCR_M_GPIODATA2 1 << GPCR_V_GPIODATA2
+#define GPCR_M_GPIODATA2 (1 << GPCR_V_GPIODATA2)
#define GPCR_V_GPIODATA3 11
-#define GPCR_M_GPIODATA3 1 << GPCR_V_GPIODATA3
+#define GPCR_M_GPIODATA3 (1 << GPCR_V_GPIODATA3)
#define GPCR_V_GPIODIR 12
-#define GPCR_M_GPIODIR 0xF << GPCR_V_GPIODIR
+#define GPCR_M_GPIODIR (0xF << GPCR_V_GPIODIR)
#define GPCR_V_GPIODIR0 12
-#define GPCR_M_GPIODIR0 1 << GPCR_V_GPIODIR0
+#define GPCR_M_GPIODIR0 (1 << GPCR_V_GPIODIR0)
#define GPCR_V_GPIODIR1 13
-#define GPCR_M_GPIODIR1 1 << GPCR_V_GPIODIR1
+#define GPCR_M_GPIODIR1 (1 << GPCR_V_GPIODIR1)
#define GPCR_V_GPIODIR2 14
-#define GPCR_M_GPIODIR2 1 << GPCR_V_GPIODIR2
+#define GPCR_M_GPIODIR2 (1 << GPCR_V_GPIODIR2)
#define GPCR_V_GPIODIR3 15
-#define GPCR_M_GPIODIR3 1 << GPCR_V_GPIODIR3
+#define GPCR_M_GPIODIR3 (1 << GPCR_V_GPIODIR3)
/*
** Refresh Period
@@ -662,39 +662,39 @@
#define PMC_SCCR_REG 0x008
#define PMC_SCCR_INIT SCCR_M_WMSKINTR
#define SCCR_V_STPGLBEN 0
-#define SCCR_M_STPGLBEN 1 << SCCR_V_STPGLBEN
+#define SCCR_M_STPGLBEN (1 << SCCR_V_STPGLBEN)
#define SCCR_V_MORESTOP 1
-#define SCCR_M_MORESTOP 1 << SCCR_V_MORESTOP
+#define SCCR_M_MORESTOP (1 << SCCR_V_MORESTOP)
#define SCCR_V_STPRELDLY 2
-#define SCCR_M_STPRELDLY 0x3 << SCCR_V_STPRELDLY
+#define SCCR_M_STPRELDLY (0x3 << SCCR_V_STPRELDLY)
#define SCCR_V_STPRELDLY0 2
-#define SCCR_M_STPRELDLY0 1 << SCCR_V_STPRELDLY0
+#define SCCR_M_STPRELDLY0 (1 << SCCR_V_STPRELDLY0)
#define SCCR_V_STPRELDLY1 3
-#define SCCR_M_STPRELDLY1 1 << SCCR_V_STPRELDLY1
+#define SCCR_M_STPRELDLY1 (1 << SCCR_V_STPRELDLY1)
#define SCCR_V_GRNTDLY 4
-#define SCCR_M_GRNTDLY 0x3 << SCCR_V_GRNTDLY
+#define SCCR_M_GRNTDLY (0x3 << SCCR_V_GRNTDLY)
#define SCCR_V_GRNTDLY0 4
-#define SCCR_M_GRNTDLY0 1 << SCCR_V_GRNTDLY0
+#define SCCR_M_GRNTDLY0 (1 << SCCR_V_GRNTDLY0)
#define SCCR_V_GRNTDLY1 5
-#define SCCR_M_GRNTDLY1 1 << SCCR_V_GRNTDLY1
+#define SCCR_M_GRNTDLY1 (1 << SCCR_V_GRNTDLY1)
#define SCCR_V_WMSKINTR 6
-#define SCCR_M_WMSKINTR 1 << SCCR_V_WMSKINTR
+#define SCCR_M_WMSKINTR (1 << SCCR_V_WMSKINTR)
#define SCCR_V_WAIT4GRNT 7
-#define SCCR_M_WAIT4GRNT 1 << SCCR_V_WAIT4GRNT
+#define SCCR_M_WAIT4GRNT (1 << SCCR_V_WAIT4GRNT)
#define SCCR_V_IOTRAPDIS 9
-#define SCCR_M_IOTRAPDIS 1 << SCCR_V_IOTRAPDIS
+#define SCCR_M_IOTRAPDIS (1 << SCCR_V_IOTRAPDIS)
#define SCCR_V_SVNCLKPLS 10
-#define SCCR_M_SVNCLKPLS 1 << SCCR_V_SVNCLKPLS
+#define SCCR_M_SVNCLKPLS (1 << SCCR_V_SVNCLKPLS)
#define SCCR_V_PCSTGSEL 11
-#define SCCR_M_PCSTGSEL 0x3 << SCCR_V_PCSTGSEL
+#define SCCR_M_PCSTGSEL (0x3 << SCCR_V_PCSTGSEL)
#define SCCR_V_PCSTGSEL0 11
-#define SCCR_M_PCSTGSEL0 1 << SCCR_V_PCSTGSEL0
+#define SCCR_M_PCSTGSEL0 (1 << SCCR_V_PCSTGSEL0)
#define SCCR_V_PCSTGSEL1 12
-#define SCCR_M_PCSTGSEL1 1 << SCCR_V_PCSTGSEL1
+#define SCCR_M_PCSTGSEL1 (1 << SCCR_V_PCSTGSEL1)
#define SCCR_V_PCSTGDIS 13
-#define SCCR_M_PCSTGDIS 1 << SCCR_V_PCSTGDIS
+#define SCCR_M_PCSTGDIS (1 << SCCR_V_PCSTGDIS)
#define SCCR_V_PCSLWEN 14
-#define SCCR_M_PCSLWEN 1 << SCCR_V_PCSLWEN
+#define SCCR_M_PCSLWEN (1 << SCCR_V_PCSLWEN)
/*
** STPCLK Release Delay
@@ -743,29 +743,29 @@
#define PMC_FOMPCR_REG 0x009
#define PMC_FOMPCR_INIT ( FOMPCR_M_PCON0 | FOMPCR_M_PCON1 )
#define FOMPCR_V_PCON 0
-#define FOMPCR_M_PCON 0x3FF << FOMPCR_V_PCON
+#define FOMPCR_M_PCON (0x3FF << FOMPCR_V_PCON)
#define FOMPCR_V_PCON0 0
-#define FOMPCR_M_PCON0 1U << FOMPCR_V_PCON0
+#define FOMPCR_M_PCON0 (1U << FOMPCR_V_PCON0)
#define FOMPCR_V_PCON1 1
-#define FOMPCR_M_PCON1 1U << FOMPCR_V_PCON1
+#define FOMPCR_M_PCON1 (1U << FOMPCR_V_PCON1)
#define FOMPCR_V_PCON2 2
-#define FOMPCR_M_PCON2 1U << FOMPCR_V_PCON2
+#define FOMPCR_M_PCON2 (1U << FOMPCR_V_PCON2)
#define FOMPCR_V_PCON3 3
-#define FOMPCR_M_PCON3 1U << FOMPCR_V_PCON3
+#define FOMPCR_M_PCON3 (1U << FOMPCR_V_PCON3)
#define FOMPCR_V_PCON4 4
-#define FOMPCR_M_PCON4 1U << FOMPCR_V_PCON4
+#define FOMPCR_M_PCON4 (1U << FOMPCR_V_PCON4)
#define FOMPCR_V_PCON5 5
-#define FOMPCR_M_PCON5 1U << FOMPCR_V_PCON5
+#define FOMPCR_M_PCON5 (1U << FOMPCR_V_PCON5)
#define FOMPCR_V_PCON6 6
-#define FOMPCR_M_PCON6 1U << FOMPCR_V_PCON6
+#define FOMPCR_M_PCON6 (1U << FOMPCR_V_PCON6)
#define FOMPCR_V_PCON7 7
-#define FOMPCR_M_PCON7 1U << FOMPCR_V_PCON7
+#define FOMPCR_M_PCON7 (1U << FOMPCR_V_PCON7)
#define FOMPCR_V_PCON8 8
-#define FOMPCR_M_PCON8 1U << FOMPCR_V_PCON8
+#define FOMPCR_M_PCON8 (1U << FOMPCR_V_PCON8)
#define FOMPCR_V_PCON9 9
-#define FOMPCR_M_PCON9 1U << FOMPCR_V_PCON9
+#define FOMPCR_M_PCON9 (1U << FOMPCR_V_PCON9)
#define FOMPCR_V_GLBLPCEN 10
-#define FOMPCR_M_GLBLPCEN 1U << FOMPCR_V_GLBLPCEN
+#define FOMPCR_M_GLBLPCEN (1U << FOMPCR_V_GLBLPCEN)
/*
**
@@ -792,31 +792,31 @@
#define PMC_DZMPCR_INIT ( DZMPCR_M_PCDZ0 | DZMPCR_M_PCDZ1 | \
DZMPCR_M_PCDZ2 )
#define DZMPCR_V_PCDZ 0
-#define DZMPCR_M_PCDZ 0x3FF << DZMPCR_V_PCDZ
+#define DZMPCR_M_PCDZ (0x3FF << DZMPCR_V_PCDZ)
#define DZMPCR_V_PCDZ0 0
-#define DZMPCR_M_PCDZ0 1 << DZMPCR_V_PCDZ0
+#define DZMPCR_M_PCDZ0 (1 << DZMPCR_V_PCDZ0)
#define DZMPCR_V_PCDZ1 1
-#define DZMPCR_M_PCDZ1 1 << DZMPCR_V_PCDZ1
+#define DZMPCR_M_PCDZ1 (1 << DZMPCR_V_PCDZ1)
#define DZMPCR_V_PCDZ2 2
-#define DZMPCR_M_PCDZ2 1 << DZMPCR_V_PCDZ2
+#define DZMPCR_M_PCDZ2 (1 << DZMPCR_V_PCDZ2)
#define DZMPCR_V_PCDZ3 3
-#define DZMPCR_M_PCDZ3 1 << DZMPCR_V_PCDZ3
+#define DZMPCR_M_PCDZ3 (1 << DZMPCR_V_PCDZ3)
#define DZMPCR_V_PCDZ4 4
-#define DZMPCR_M_PCDZ4 1 << DZMPCR_V_PCDZ4
+#define DZMPCR_M_PCDZ4 (1 << DZMPCR_V_PCDZ4)
#define DZMPCR_V_PCDZ5 5
-#define DZMPCR_M_PCDZ5 1 << DZMPCR_V_PCDZ5
+#define DZMPCR_M_PCDZ5 (1 << DZMPCR_V_PCDZ5)
#define DZMPCR_V_PCDZ6 6
-#define DZMPCR_M_PCDZ6 1 << DZMPCR_V_PCDZ6
+#define DZMPCR_M_PCDZ6 (1 << DZMPCR_V_PCDZ6)
#define DZMPCR_V_PCDZ7 7
-#define DZMPCR_M_PCDZ7 1 << DZMPCR_V_PCDZ7
+#define DZMPCR_M_PCDZ7 (1 << DZMPCR_V_PCDZ7)
#define DZMPCR_V_PCDZ8 8
-#define DZMPCR_M_PCDZ8 1 << DZMPCR_V_PCDZ8
+#define DZMPCR_M_PCDZ8 (1 << DZMPCR_V_PCDZ8)
#define DZMPCR_V_PCDZ9 9
-#define DZMPCR_M_PCDZ9 1 << DZMPCR_V_PCDZ9
+#define DZMPCR_M_PCDZ9 (1 << DZMPCR_V_PCDZ9)
#define DZMPCR_V_SPNDDLY 10
-#define DZMPCR_M_SPNDDLY 1 << DZMPCR_V_SPNDDLY
+#define DZMPCR_M_SPNDDLY (1 << DZMPCR_V_SPNDDLY)
#define DZMPCR_V_STRTDLY 11
-#define DZMPCR_M_STRTDLY 1 << DZMPCR_V_STRTDLY
+#define DZMPCR_M_STRTDLY (1 << DZMPCR_V_STRTDLY)
/*
**
@@ -847,43 +847,43 @@
SLPMPCR_M_PCSLP2 | LBFLSHRAT_2HZ | \
LBFLSHDUR_62PT5MS )
#define SLPMPCR_V_PCSLP 0
-#define SLPMPCR_M_PCSLP 0x3FF << SLPMPCR_V_PCSLP
+#define SLPMPCR_M_PCSLP (0x3FF << SLPMPCR_V_PCSLP)
#define SLPMPCR_V_PCSLP0 0
-#define SLPMPCR_M_PCSLP0 1 << SLPMPCR_V_PCSLP0
+#define SLPMPCR_M_PCSLP0 (1 << SLPMPCR_V_PCSLP0)
#define SLPMPCR_V_PCSLP1 1
-#define SLPMPCR_M_PCSLP1 1 << SLPMPCR_V_PCSLP1
+#define SLPMPCR_M_PCSLP1 (1 << SLPMPCR_V_PCSLP1)
#define SLPMPCR_V_PCSLP2 2
-#define SLPMPCR_M_PCSLP2 1 << SLPMPCR_V_PCSLP2
+#define SLPMPCR_M_PCSLP2 (1 << SLPMPCR_V_PCSLP2)
#define SLPMPCR_V_PCSLP3 3
-#define SLPMPCR_M_PCSLP3 1 << SLPMPCR_V_PCSLP3
+#define SLPMPCR_M_PCSLP3 (1 << SLPMPCR_V_PCSLP3)
#define SLPMPCR_V_PCSLP4 4
-#define SLPMPCR_M_PCSLP4 1 << SLPMPCR_V_PCSLP4
+#define SLPMPCR_M_PCSLP4 (1 << SLPMPCR_V_PCSLP4)
#define SLPMPCR_V_PCSLP5 5
-#define SLPMPCR_M_PCSLP5 1 << SLPMPCR_V_PCSLP5
+#define SLPMPCR_M_PCSLP5 (1 << SLPMPCR_V_PCSLP5)
#define SLPMPCR_V_PCSLP6 6
-#define SLPMPCR_M_PCSLP6 1 << SLPMPCR_V_PCSLP6
+#define SLPMPCR_M_PCSLP6 (1 << SLPMPCR_V_PCSLP6)
#define SLPMPCR_V_PCSLP7 7
-#define SLPMPCR_M_PCSLP7 1 << SLPMPCR_V_PCSLP7
+#define SLPMPCR_M_PCSLP7 (1 << SLPMPCR_V_PCSLP7)
#define SLPMPCR_V_PCSLP8 8
-#define SLPMPCR_M_PCSLP8 1 << SLPMPCR_V_PCSLP8
+#define SLPMPCR_M_PCSLP8 (1 << SLPMPCR_V_PCSLP8)
#define SLPMPCR_V_PCSLP9 9
-#define SLPMPCR_M_PCSLP9 1 << SLPMPCR_V_PCSLP9
+#define SLPMPCR_M_PCSLP9 (1 << SLPMPCR_V_PCSLP9)
#define SLPMPCR_V_LBLEDFLSH 10
-#define SLPMPCR_M_LBLEDFLSH 1 << SLPMPCR_V_LBLEDFLSH
+#define SLPMPCR_M_LBLEDFLSH (1 << SLPMPCR_V_LBLEDFLSH)
#define SLPMPCR_V_LBFLSHRAT 11
-#define SLPMPCR_M_LBFLSHRAT 0x3 << SLPMPCR_V_LBFLSHRAT
+#define SLPMPCR_M_LBFLSHRAT (0x3 << SLPMPCR_V_LBFLSHRAT)
#define SLPMPCR_V_LBFLSHRAT0 11
-#define SLPMPCR_M_LBFLSHRAT0 1 << SLPMPCR_V_LBFLSHRAT0
+#define SLPMPCR_M_LBFLSHRAT0 (1 << SLPMPCR_V_LBFLSHRAT0)
#define SLPMPCR_V_LBFLSHRAT1 12
-#define SLPMPCR_M_LBFLSHRAT1 1 << SLPMPCR_V_LBFLSHRAT1
+#define SLPMPCR_M_LBFLSHRAT1 (1 << SLPMPCR_V_LBFLSHRAT1)
#define SLPMPCR_V_LBFLSHDUR 13
-#define SLPMPCR_M_LBFLSHDUR 0x3 << SLPMPCR_V_LBFLSHDUR
+#define SLPMPCR_M_LBFLSHDUR (0x3 << SLPMPCR_V_LBFLSHDUR)
#define SLPMPCR_V_LBFLSHDUR0 13
-#define SLPMPCR_M_LBFLSHDUR0 1 << SLPMPCR_V_LBFLSHDUR0
+#define SLPMPCR_M_LBFLSHDUR0 (1 << SLPMPCR_V_LBFLSHDUR0)
#define SLPMPCR_V_LBFLSHDUR1 14
-#define SLPMPCR_M_LBFLSHDUR1 1 << SLPMPCR_V_LBFLSHDUR1
+#define SLPMPCR_M_LBFLSHDUR1 (1 << SLPMPCR_V_LBFLSHDUR1)
#define SLPMPCR_V_VLBFLSHEN 15
-#define SLPMPCR_M_VLBFLSHEN 1 << SLPMPCR_V_VLBFLSHEN
+#define SLPMPCR_M_VLBFLSHEN (1 << SLPMPCR_V_VLBFLSHEN)
/*
** Low Battery LED Flash Rate Selects
@@ -932,41 +932,41 @@
SPNDMPCR_M_PCSPND2 | SPFLSHRAT_2HZ | \
SPFLSHDUR_62PT5MS )
#define SPNDMPCR_V_PCSPND 0
-#define SPNDMPCR_M_PCSPND 0x3FF << SPNDMPCR_V_PCSPND
+#define SPNDMPCR_M_PCSPND (0x3FF << SPNDMPCR_V_PCSPND)
#define SPNDMPCR_V_PCSPND0 0
-#define SPNDMPCR_M_PCSPND0 1 << SPNDMPCR_V_PCSPND0
+#define SPNDMPCR_M_PCSPND0 (1 << SPNDMPCR_V_PCSPND0)
#define SPNDMPCR_V_PCSPND1 1
-#define SPNDMPCR_M_PCSPND1 1 << SPNDMPCR_V_PCSPND1
+#define SPNDMPCR_M_PCSPND1 (1 << SPNDMPCR_V_PCSPND1)
#define SPNDMPCR_V_PCSPND2 2
-#define SPNDMPCR_M_PCSPND2 1 << SPNDMPCR_V_PCSPND2
+#define SPNDMPCR_M_PCSPND2 (1 << SPNDMPCR_V_PCSPND2)
#define SPNDMPCR_V_PCSPND3 3
-#define SPNDMPCR_M_PCSPND3 1 << SPNDMPCR_V_PCSPND3
+#define SPNDMPCR_M_PCSPND3 (1 << SPNDMPCR_V_PCSPND3)
#define SPNDMPCR_V_PCSPND4 4
-#define SPNDMPCR_M_PCSPND4 1 << SPNDMPCR_V_PCSPND4
+#define SPNDMPCR_M_PCSPND4 (1 << SPNDMPCR_V_PCSPND4)
#define SPNDMPCR_V_PCSPND5 5
-#define SPNDMPCR_M_PCSPND5 1 << SPNDMPCR_V_PCSPND5
+#define SPNDMPCR_M_PCSPND5 (1 << SPNDMPCR_V_PCSPND5)
#define SPNDMPCR_V_PCSPND6 6
-#define SPNDMPCR_M_PCSPND6 1 << SPNDMPCR_V_PCSPND6
+#define SPNDMPCR_M_PCSPND6 (1 << SPNDMPCR_V_PCSPND6)
#define SPNDMPCR_V_PCSPND7 7
-#define SPNDMPCR_M_PCSPND7 1 << SPNDMPCR_V_PCSPND7
+#define SPNDMPCR_M_PCSPND7 (1 << SPNDMPCR_V_PCSPND7)
#define SPNDMPCR_V_PCSPND8 8
-#define SPNDMPCR_M_PCSPND8 1 << SPNDMPCR_V_PCSPND8
+#define SPNDMPCR_M_PCSPND8 (1 << SPNDMPCR_V_PCSPND8)
#define SPNDMPCR_V_PCSPND9 9
-#define SPNDMPCR_M_PCSPND9 1 << SPNDMPCR_V_PCSPND9
+#define SPNDMPCR_M_PCSPND9 (1 << SPNDMPCR_V_PCSPND9)
#define SPNDMPCR_V_SPLEDFLSH 10
-#define SPNDMPCR_M_SPLEDFLSH 1 << SPNDMPCR_V_SPLEDFLSH
+#define SPNDMPCR_M_SPLEDFLSH (1 << SPNDMPCR_V_SPLEDFLSH)
#define SPNDMPCR_V_SPFLSHRAT 11
-#define SPNDMPCR_M_SPFLSHRAT 0x3 << SPNDMPCR_V_SPFLSHRAT
+#define SPNDMPCR_M_SPFLSHRAT (0x3 << SPNDMPCR_V_SPFLSHRAT)
#define SPNDMPCR_V_SPFLSHRAT0 11
-#define SPNDMPCR_M_SPFLSHRAT0 1 << SPNDMPCR_V_SPFLSHRAT0
+#define SPNDMPCR_M_SPFLSHRAT0 (1 << SPNDMPCR_V_SPFLSHRAT0)
#define SPNDMPCR_V_SPFLSHRAT1 12
-#define SPNDMPCR_M_SPFLSHRAT1 1 << SPNDMPCR_V_SPFLSHRAT1
+#define SPNDMPCR_M_SPFLSHRAT1 (1 << SPNDMPCR_V_SPFLSHRAT1)
#define SPNDMPCR_V_SPFLSHDUR 13
-#define SPNDMPCR_M_SPFLSHDUR 0x3 << SPNDMPCR_V_SPFLSHDUR
+#define SPNDMPCR_M_SPFLSHDUR (0x3 << SPNDMPCR_V_SPFLSHDUR)
#define SPNDMPCR_V_SPFLSHDUR0 13
-#define SPNDMPCR_M_SPFLSHDUR0 1 << SPNDMPCR_V_SPFLSHDUR0
+#define SPNDMPCR_M_SPFLSHDUR0 (1 << SPNDMPCR_V_SPFLSHDUR0)
#define SPNDMPCR_V_SPFLSHDUR1 14
-#define SPNDMPCR_M_SPFLSHDUR1 1 << SPNDMPCR_V_SPFLSHDUR1
+#define SPNDMPCR_M_SPFLSHDUR1 (1 << SPNDMPCR_V_SPFLSHDUR1)
/*
** Suspend LED Flash Rate Selects
@@ -1011,41 +1011,41 @@
#define PMC_TIMERR_REG 0x00D
#define PMC_TIMERR_INIT 0x0000
#define TIMERR_V_GENTMR 0
-#define TIMERR_M_GENTMR 0xF << TIMERR_V_GENTMR
+#define TIMERR_M_GENTMR (0xF << TIMERR_V_GENTMR)
#define TIMERR_V_GENTMR0 0
-#define TIMERR_M_GENTMR0 1 << TIMERR_V_GENTMR0
+#define TIMERR_M_GENTMR0 (1 << TIMERR_V_GENTMR0)
#define TIMERR_V_GENTMR1 1
-#define TIMERR_M_GENTMR1 1 << TIMERR_V_GENTMR1
+#define TIMERR_M_GENTMR1 (1 << TIMERR_V_GENTMR1)
#define TIMERR_V_GENTMR2 2
-#define TIMERR_M_GENTMR2 1 << TIMERR_V_GENTMR2
+#define TIMERR_M_GENTMR2 (1 << TIMERR_V_GENTMR2)
#define TIMERR_V_GENTMR3 3
-#define TIMERR_M_GENTMR3 1 << TIMERR_V_GENTMR3
+#define TIMERR_M_GENTMR3 (1 << TIMERR_V_GENTMR3)
#define TIMERR_V_SPMDTMR 4
-#define TIMERR_M_SPMDTMR 0x7 << TIMERR_V_SPMDTMR
+#define TIMERR_M_SPMDTMR (0x7 << TIMERR_V_SPMDTMR)
#define TIMERR_V_SPMDTMR0 4
-#define TIMERR_M_SPMDTMR0 1 << TIMERR_V_SPMDTMR0
+#define TIMERR_M_SPMDTMR0 (1 << TIMERR_V_SPMDTMR0)
#define TIMERR_V_SPMDTMR1 5
-#define TIMERR_M_SPMDTMR1 1 << TIMERR_V_SPMDTMR1
+#define TIMERR_M_SPMDTMR1 (1 << TIMERR_V_SPMDTMR1)
#define TIMERR_V_SPMDTMR2 6
-#define TIMERR_M_SPMDTMR2 1 << TIMERR_V_SPMDTMR2
+#define TIMERR_M_SPMDTMR2 (1 << TIMERR_V_SPMDTMR2)
#define TIMERR_V_SLPTMR 7
-#define TIMERR_M_SLPTMR 0x7 << TIMERR_V_SLPTMR
+#define TIMERR_M_SLPTMR (0x7 << TIMERR_V_SLPTMR)
#define TIMERR_V_SLPTMR0 7
-#define TIMERR_M_SLPTMR0 1 << TIMERR_V_SLPTMR0
+#define TIMERR_M_SLPTMR0 (1 << TIMERR_V_SLPTMR0)
#define TIMERR_V_SLPTMR1 8
-#define TIMERR_M_SLPTMR1 1 << TIMERR_V_SLPTMR1
+#define TIMERR_M_SLPTMR1 (1 << TIMERR_V_SLPTMR1)
#define TIMERR_V_SLPTMR2 9
-#define TIMERR_M_SLPTMR2 1 << TIMERR_V_SLPTMR2
+#define TIMERR_M_SLPTMR2 (1 << TIMERR_V_SLPTMR2)
#define TIMERR_V_DZTMR 10
-#define TIMERR_M_DZTMR 0x7 << TIMERR_V_DZTMR
+#define TIMERR_M_DZTMR (0x7 << TIMERR_V_DZTMR)
#define TIMERR_V_DZTMR0 10
-#define TIMERR_M_DZTMR0 1 << TIMERR_V_DZTMR0
+#define TIMERR_M_DZTMR0 (1 << TIMERR_V_DZTMR0)
#define TIMERR_V_DZTMR1 11
-#define TIMERR_M_DZTMR1 1 << TIMERR_V_DZTMR1
+#define TIMERR_M_DZTMR1 (1 << TIMERR_V_DZTMR1)
#define TIMERR_V_DZTMR2 12
-#define TIMERR_M_DZTMR2 1 << TIMERR_V_DZTMR2
+#define TIMERR_M_DZTMR2 (1 << TIMERR_V_DZTMR2)
#define TIMERR_V_GTRSTPADIS 15
-#define TIMERR_M_GTRSTPADIS 1 << TIMERR_V_GTRSTPADIS
+#define TIMERR_M_GTRSTPADIS (1 << TIMERR_V_GTRSTPADIS)
/*
** Generic Timer (Seconds)
@@ -1131,25 +1131,25 @@
PMCMCR1_M_WAKE1MSK | PMCMCR1_M_WMSKRING | \
PMCMCR1_M_WMSKRTC | PMCMCR1_M_WMSKTMR )
#define PMCMCR1_V_GPCTSEL0 2
-#define PMCMCR1_M_GPCTSEL0 1 << PMCMCR1_V_GPCTSEL0
+#define PMCMCR1_M_GPCTSEL0 (1 << PMCMCR1_V_GPCTSEL0)
#define PMCMCR1_V_GPCTSEL1 3
-#define PMCMCR1_M_GPCTSEL1 1 << PMCMCR1_V_GPCTSEL1
+#define PMCMCR1_M_GPCTSEL1 (1 << PMCMCR1_V_GPCTSEL1)
#define PMCMCR1_V_GPCTEN 4
-#define PMCMCR1_M_GPCTEN 1 << PMCMCR1_V_GPCTEN
+#define PMCMCR1_M_GPCTEN (1 << PMCMCR1_V_GPCTEN)
#define PMCMCR1_V_WMSKVLBNAC 5
-#define PMCMCR1_M_WMSKVLBNAC 1 << PMCMCR1_V_WMSKVLBNAC
+#define PMCMCR1_M_WMSKVLBNAC (1 << PMCMCR1_V_WMSKVLBNAC)
#define PMCMCR1_V_WAKE0MSK 6
-#define PMCMCR1_M_WAKE0MSK 1 << PMCMCR1_V_WAKE0MSK
+#define PMCMCR1_M_WAKE0MSK (1 << PMCMCR1_V_WAKE0MSK)
#define PMCMCR1_V_WAKE1MSK 7
-#define PMCMCR1_M_WAKE1MSK 1 << PMCMCR1_V_WAKE1MSK
+#define PMCMCR1_M_WAKE1MSK (1 << PMCMCR1_V_WAKE1MSK)
#define PMCMCR1_V_WMSKRING 8
-#define PMCMCR1_M_WMSKRING 1 << PMCMCR1_V_WMSKRING
+#define PMCMCR1_M_WMSKRING (1 << PMCMCR1_V_WMSKRING)
#define PMCMCR1_V_WMSKRTC 9
-#define PMCMCR1_M_WMSKRTC 1 << PMCMCR1_V_WMSKRTC
+#define PMCMCR1_M_WMSKRTC (1 << PMCMCR1_V_WMSKRTC)
#define PMCMCR1_V_WMSKTMR 11
-#define PMCMCR1_M_WMSKTMR 1 << PMCMCR1_V_WMSKTMR
+#define PMCMCR1_M_WMSKTMR (1 << PMCMCR1_V_WMSKTMR)
#define PMCMCR1_V_PRDCTID 12
-#define PMCMCR1_M_PRDCTID 0xF << PMCMCR1_V_PRDCTID
+#define PMCMCR1_M_PRDCTID (0xF << PMCMCR1_V_PRDCTID)
/*
**
@@ -1229,27 +1229,27 @@
#define PMC_DBCR_REG 0x012
#define PMC_DBCR_INIT 0x0000
#define DBCR_V_DBDIS0 0
-#define DBCR_M_DBDIS0 1 << DBCR_V_DBDIS0
+#define DBCR_M_DBDIS0 (1 << DBCR_V_DBDIS0)
#define DBCR_V_DBDIS1 2
-#define DBCR_M_DBDIS1 1 << DBCR_V_DBDIS1
+#define DBCR_M_DBDIS1 (1 << DBCR_V_DBDIS1)
#define DBCR_V_DBTMDR1 3
-#define DBCR_M_DBTMDR1 1 << DBCR_V_DBTMDR1
+#define DBCR_M_DBTMDR1 (1 << DBCR_V_DBTMDR1)
#define DBCR_V_DBDIS2 4
-#define DBCR_M_DBDIS2 1 << DBCR_V_DBDIS2
+#define DBCR_M_DBDIS2 (1 << DBCR_V_DBDIS2)
#define DBCR_V_DBTMDR2 5
-#define DBCR_M_DBTMDR2 1 << DBCR_V_DBTMDR2
+#define DBCR_M_DBTMDR2 (1 << DBCR_V_DBTMDR2)
#define DBCR_V_DBDIS3 6
-#define DBCR_M_DBDIS3 1 << DBCR_V_DBDIS3
+#define DBCR_M_DBDIS3 (1 << DBCR_V_DBDIS3)
#define DBCR_V_DBTMDR3 7
-#define DBCR_M_DBTMDR3 1 << DBCR_V_DBTMDR3
+#define DBCR_M_DBTMDR3 (1 << DBCR_V_DBTMDR3)
#define DBCR_V_WAKE0DBDIS 12
-#define DBCR_M_WAKE0DBDIS 1 << DBCR_V_WAKE0DBDIS
+#define DBCR_M_WAKE0DBDIS (1 << DBCR_V_WAKE0DBDIS)
#define DBCR_V_WAKE0DBTMDR 13
-#define DBCR_M_WAKE0DBTMDR 1 << DBCR_V_WAKE0DBTMDR
+#define DBCR_M_WAKE0DBTMDR (1 << DBCR_V_WAKE0DBTMDR)
#define DBCR_V_WAKE1DBDIS 14
-#define DBCR_M_WAKE1DBDIS 1 << DBCR_V_WAKE1DBDIS
+#define DBCR_M_WAKE1DBDIS (1 << DBCR_V_WAKE1DBDIS)
#define DBCR_V_WAKE1DBTMDR 15
-#define DBCR_M_WAKE1DBTMDR 1 << DBCR_V_WAKE1DBTMDR
+#define DBCR_M_WAKE1DBTMDR (1 << DBCR_V_WAKE1DBTMDR)
/*
**
@@ -1276,25 +1276,25 @@
PMCMCR2_M_PMCRSTEN | \
PMCMCR2_M_SPSRESETDIS )
#define PMCMCR2_V_GPCTSEL0 1
-#define PMCMCR2_M_GPCTSEL0 1 << PMCMCR2_V_SMIRDYEN
+#define PMCMCR2_M_GPCTSEL0 (1 << PMCMCR2_V_SMIRDYEN)
#define PMCMCR2_V_PWRGDSTBYDIS 2
-#define PMCMCR2_M_PWRGDSTBYDIS 1 << PMCMCR2_V_PWRGDSTBYDIS
+#define PMCMCR2_M_PWRGDSTBYDIS (1 << PMCMCR2_V_PWRGDSTBYDIS)
#define PMCMCR2_V_GLBLRSTEN 3
-#define PMCMCR2_M_GLBLRSTEN 1 << PMCMCR2_V_GLBLRSTEN
+#define PMCMCR2_M_GLBLRSTEN (1 << PMCMCR2_V_GLBLRSTEN)
#define PMCMCR2_V_PMCRSTEN 4
-#define PMCMCR2_M_PMCRSTEN 1 << PMCMCR2_V_PMCRSTEN
+#define PMCMCR2_M_PMCRSTEN (1 << PMCMCR2_V_PMCRSTEN)
#define PMCMCR2_V_SPSRESETDIS 7
-#define PMCMCR2_M_SPSRESETDIS 1 << PMCMCR2_V_SPSRESETDIS
+#define PMCMCR2_M_SPSRESETDIS (1 << PMCMCR2_V_SPSRESETDIS)
#define PMCMCR2_V_SPRSTDRVDIS 8
-#define PMCMCR2_M_SPRSTDRVDIS 1 << PMCMCR2_V_SPRSTDRVDIS
+#define PMCMCR2_M_SPRSTDRVDIS (1 << PMCMCR2_V_SPRSTDRVDIS)
#define PMCMCR2_V_WAKE0TOGL 9
-#define PMCMCR2_M_WAKE0TOGL 1 << PMCMCR2_V_WAKE0TOGL
+#define PMCMCR2_M_WAKE0TOGL (1 << PMCMCR2_V_WAKE0TOGL)
#define PMCMCR2_V_WAKE1TOGL 10
-#define PMCMCR2_M_WAKE1TOGL 1 << PMCMCR2_V_WAKE1TOGL
+#define PMCMCR2_M_WAKE1TOGL (1 << PMCMCR2_V_WAKE1TOGL)
#define PMCMCR2_V_SWTCHEN 14
-#define PMCMCR2_M_SWTCHEN 1 << PMCMCR2_V_SWTCHEN
+#define PMCMCR2_M_SWTCHEN (1 << PMCMCR2_V_SWTCHEN)
#define PMCMCR2_V_RSTCPUFLG 15
-#define PMCMCR2_M_RSTCPUFLG 1 << PMCMCR2_V_RSTCPUFLG
+#define PMCMCR2_M_RSTCPUFLG (1 << PMCMCR2_V_RSTCPUFLG)
/*
**
@@ -1323,41 +1323,41 @@
GPIOCR2_M_GPIOBDIR1 | GPIOCR2_M_GPIOCDATA0 | \
GPIOCR2_M_GPIOCDIR0 | GPIOCR2_M_GPIOCDIR1 )
#define GPIOCR2_V_GPIOADATA 0
-#define GPIOCR2_M_GPIOADATA 0x3 << GPIOCR2_V_GPIOADATA
+#define GPIOCR2_M_GPIOADATA (0x3 << GPIOCR2_V_GPIOADATA)
#define GPIOCR2_V_GPIOADATA0 0
-#define GPIOCR2_M_GPIOADATA0 1 << GPIOCR2_V_GPIOADATA0
+#define GPIOCR2_M_GPIOADATA0 (1 << GPIOCR2_V_GPIOADATA0)
#define GPIOCR2_V_GPIOADATA1 1
-#define GPIOCR2_M_GPIOADATA1 1 << GPIOCR2_V_GPIOADATA1
+#define GPIOCR2_M_GPIOADATA1 (1 << GPIOCR2_V_GPIOADATA1)
#define GPIOCR2_V_GPIOADIR 2
-#define GPIOCR2_M_GPIOADIR 0x3 << GPIOCR2_V_GPIOADIR
+#define GPIOCR2_M_GPIOADIR (0x3 << GPIOCR2_V_GPIOADIR)
#define GPIOCR2_V_GPIOADIR0 2
-#define GPIOCR2_M_GPIOADIR0 1 << GPIOCR2_V_GPIOADIR0
+#define GPIOCR2_M_GPIOADIR0 (1 << GPIOCR2_V_GPIOADIR0)
#define GPIOCR2_V_GPIOADIR1 3
-#define GPIOCR2_M_GPIOADIR1 1 << GPIOCR2_V_GPIOADIR1
+#define GPIOCR2_M_GPIOADIR1 (1 << GPIOCR2_V_GPIOADIR1)
#define GPIOCR2_V_GPIOBDATA 4
-#define GPIOCR2_M_GPIOBDATA 0x3 << GPIOCR2_V_GPIOBDATA
+#define GPIOCR2_M_GPIOBDATA (0x3 << GPIOCR2_V_GPIOBDATA)
#define GPIOCR2_V_GPIOBDATA0 4
-#define GPIOCR2_M_GPIOBDATA0 1 << GPIOCR2_V_GPIOBDATA0
+#define GPIOCR2_M_GPIOBDATA0 (1 << GPIOCR2_V_GPIOBDATA0)
#define GPIOCR2_V_GPIOBDATA1 5
-#define GPIOCR2_M_GPIOBDATA1 1 << GPIOCR2_V_GPIOBDATA1
+#define GPIOCR2_M_GPIOBDATA1 (1 << GPIOCR2_V_GPIOBDATA1)
#define GPIOCR2_V_GPIOBDIR 6
-#define GPIOCR2_M_GPIOBDIR 0x3 << GPIOCR2_V_GPIOBDIR
+#define GPIOCR2_M_GPIOBDIR (0x3 << GPIOCR2_V_GPIOBDIR)
#define GPIOCR2_V_GPIOBDIR0 6
-#define GPIOCR2_M_GPIOBDIR0 1 << GPIOCR2_V_GPIOBDIR0
+#define GPIOCR2_M_GPIOBDIR0 (1 << GPIOCR2_V_GPIOBDIR0)
#define GPIOCR2_V_GPIOBDIR1 7
-#define GPIOCR2_M_GPIOBDIR1 1 << GPIOCR2_V_GPIOBDIR1
+#define GPIOCR2_M_GPIOBDIR1 (1 << GPIOCR2_V_GPIOBDIR1)
#define GPIOCR2_V_GPIOCDATA 8
-#define GPIOCR2_M_GPIOCDATA 0x3 << GPIOCR2_V_GPIOCDATA
+#define GPIOCR2_M_GPIOCDATA (0x3 << GPIOCR2_V_GPIOCDATA)
#define GPIOCR2_V_GPIOCDATA0 8
-#define GPIOCR2_M_GPIOCDATA0 1 << GPIOCR2_V_GPIOCDATA0
+#define GPIOCR2_M_GPIOCDATA0 (1 << GPIOCR2_V_GPIOCDATA0)
#define GPIOCR2_V_GPIOCDATA1 9
-#define GPIOCR2_M_GPIOCDATA1 1 << GPIOCR2_V_GPIOCDATA1
+#define GPIOCR2_M_GPIOCDATA1 (1 << GPIOCR2_V_GPIOCDATA1)
#define GPIOCR2_V_GPIOCDIR 10
-#define GPIOCR2_M_GPIOCDIR 0x3 << GPIOCR2_V_GPIOCDIR
+#define GPIOCR2_M_GPIOCDIR (0x3 << GPIOCR2_V_GPIOCDIR)
#define GPIOCR2_V_GPIOCDIR0 10
-#define GPIOCR2_M_GPIOCDIR0 1 << GPIOCR2_V_GPIOCDIR0
+#define GPIOCR2_M_GPIOCDIR0 (1 << GPIOCR2_V_GPIOCDIR0)
#define GPIOCR2_V_GPIOCDIR1 11
-#define GPIOCR2_M_GPIOCDIR1 1 << GPIOCR2_V_GPIOCDIR1
+#define GPIOCR2_M_GPIOCDIR1 (1 << GPIOCR2_V_GPIOCDIR1)
/*
**
@@ -1389,29 +1389,29 @@
LKCR_M_BMLCDIS | LKCR_M_PC03LCDIS | \
LKCR_M_PWRGDLCDIS | LKCR_M_LCDIS )
#define LKCR_V_CPULCDIS 0
-#define LKCR_M_CPULCDIS 1 << LKCR_V_CPULCDIS
+#define LKCR_M_CPULCDIS (1 << LKCR_V_CPULCDIS)
#define LKCR_V_DRAMLCDIS 1
-#define LKCR_M_DRAMLCDIS 1 << LKCR_V_DRAMLCDIS
+#define LKCR_M_DRAMLCDIS (1 << LKCR_V_DRAMLCDIS)
#define LKCR_V_L2CACHELCDIS 2
-#define LKCR_M_L2CACHELCDIS 1 << LKCR_V_L2CACHELCDIS
+#define LKCR_M_L2CACHELCDIS (1 << LKCR_V_L2CACHELCDIS)
#define LKCR_V_ATLCDIS 3
-#define LKCR_M_ATLCDIS 1 << LKCR_V_ATLCDIS
+#define LKCR_M_ATLCDIS (1 << LKCR_V_ATLCDIS)
#define LKCR_V_BBUSLCDIS 4
-#define LKCR_M_BBUSLCDIS 1 << LKCR_V_BBUSLCDIS
+#define LKCR_M_BBUSLCDIS (1 << LKCR_V_BBUSLCDIS)
#define LKCR_V_GPIOLCDIS 5
-#define LKCR_M_GPIOLCDIS 1 << LKCR_V_GPIOLCDIS
+#define LKCR_M_GPIOLCDIS (1 << LKCR_V_GPIOLCDIS)
#define LKCR_V_PC49LCDIS 6
-#define LKCR_M_PC49LCDIS 1 << LKCR_V_PC49LCDIS
+#define LKCR_M_PC49LCDIS (1 << LKCR_V_PC49LCDIS)
#define LKCR_V_LEDLCDIS 7
-#define LKCR_M_LEDLCDIS 1 << LKCR_V_LEDLCDIS
+#define LKCR_M_LEDLCDIS (1 << LKCR_V_LEDLCDIS)
#define LKCR_V_BMLCDIS 8
-#define LKCR_M_BMLCDIS 1 << LKCR_V_BMLCDIS
+#define LKCR_M_BMLCDIS (1 << LKCR_V_BMLCDIS)
#define LKCR_V_PC03LCDIS 9
-#define LKCR_M_PC03LCDIS 1 << LKCR_V_PC03LCDIS
+#define LKCR_M_PC03LCDIS (1 << LKCR_V_PC03LCDIS)
#define LKCR_V_PWRGDLCDIS 14
-#define LKCR_M_PWRGDLCDIS 1 << LKCR_V_PWRGDLCDIS
+#define LKCR_M_PWRGDLCDIS (1 << LKCR_V_PWRGDLCDIS)
#define LKCR_V_LCDIS 15
-#define LKCR_M_LCDIS 1 << LKCR_V_LCDIS
+#define LKCR_M_LCDIS (1 << LKCR_V_LCDIS)
/*
**
@@ -1430,13 +1430,13 @@
#define PMC_SEQMR1_REG 0x016
#define PMC_SEQMR1_INIT 0x0000
#define SEQMR1_V_DISCREADS 11
-#define SEQMR1_M_DISCREADS 1 << SEQMR1_V_DISCREADS
+#define SEQMR1_M_DISCREADS (1 << SEQMR1_V_DISCREADS)
#define SEQMR1_V_FRCBLASTDIS 12
-#define SEQMR1_M_FRCBLASTDIS 1 << SEQMR1_V_FRCBLASTDIS
+#define SEQMR1_M_FRCBLASTDIS (1 << SEQMR1_V_FRCBLASTDIS)
#define SEQMR1_V_P92B3EN 14
-#define SEQMR1_M_P92B3EN 1 << SEQMR1_V_P92B3EN
+#define SEQMR1_M_P92B3EN (1 << SEQMR1_V_P92B3EN)
#define SEQMR1_V_SWTSTBYDIS 15
-#define SEQMR1_M_SWTSTBYDIS 1 << SEQMR1_V_SWTSTBYDIS
+#define SEQMR1_M_SWTSTBYDIS (1 << SEQMR1_V_SWTSTBYDIS)
/*
**
@@ -1454,11 +1454,11 @@
#define PMC_SEQMR2_REG 0x017
#define PMC_SEQMR2_INIT 0x0000
#define SEQMR2_V_DLYWCASEN 0
-#define SEQMR2_M_DLYWCASEN 1 << SEQMR2_V_DLYWCASEN
+#define SEQMR2_M_DLYWCASEN (1 << SEQMR2_V_DLYWCASEN)
#define SEQMR2_V_SMMWTEN 1
-#define SEQMR2_M_SMMWTEN 1 << SEQMR2_V_SMMWTEN
+#define SEQMR2_M_SMMWTEN (1 << SEQMR2_V_SMMWTEN)
#define SEQMR2_V_STATICSPNDEN 2
-#define SEQMR2_M_STATICSPNDEN 1 << SEQMR2_V_STATICSPNDEN
+#define SEQMR2_M_STATICSPNDEN (1 << SEQMR2_V_STATICSPNDEN)
/*
**
@@ -1487,25 +1487,25 @@
SAMR_M_SAMSKEACT0 | SAMR_M_SAMSKEACT1 | \
SAMR_M_SAMSKEACT2 | SAMR_M_SAMSKEACT3 )
#define SAMR_V_SAMSKVID 0
-#define SAMR_M_SAMSKVID 1 << SAMR_V_SAMSKVID
+#define SAMR_M_SAMSKVID (1 << SAMR_V_SAMSKVID)
#define SAMR_V_SAMSKKBD 3
-#define SAMR_M_SAMSKKBD 1 << SAMR_V_SAMSKKBD
+#define SAMR_M_SAMSKKBD (1 << SAMR_V_SAMSKKBD)
#define SAMR_V_SAMSKPROG0 6
-#define SAMR_M_SAMSKPROG0 1 << SAMR_V_SAMSKPROG0
+#define SAMR_M_SAMSKPROG0 (1 << SAMR_V_SAMSKPROG0)
#define SAMR_V_SAMSKPROG1 7
-#define SAMR_M_SAMSKPROG1 1 << SAMR_V_SAMSKPROG1
+#define SAMR_M_SAMSKPROG1 (1 << SAMR_V_SAMSKPROG1)
#define SAMR_V_SAMSKPROG2 8
-#define SAMR_M_SAMSKPROG2 1 << SAMR_V_SAMSKPROG2
+#define SAMR_M_SAMSKPROG2 (1 << SAMR_V_SAMSKPROG2)
#define SAMR_V_SAMSKPROG3 9
-#define SAMR_M_SAMSKPROG3 1 << SAMR_V_SAMSKPROG3
+#define SAMR_M_SAMSKPROG3 (1 << SAMR_V_SAMSKPROG3)
#define SAMR_V_SAMSKEACT0 12
-#define SAMR_M_SAMSKEACT0 1 << SAMR_V_SAMSKEACT0
+#define SAMR_M_SAMSKEACT0 (1 << SAMR_V_SAMSKEACT0)
#define SAMR_V_SAMSKEACT1 13
-#define SAMR_M_SAMSKEACT1 1 << SAMR_V_SAMSKEACT1
+#define SAMR_M_SAMSKEACT1 (1 << SAMR_V_SAMSKEACT1)
#define SAMR_V_SAMSKEACT2 14
-#define SAMR_M_SAMSKEACT2 1 << SAMR_V_SAMSKEACT2
+#define SAMR_M_SAMSKEACT2 (1 << SAMR_V_SAMSKEACT2)
#define SAMR_V_SAMSKEACT3 15
-#define SAMR_M_SAMSKEACT3 1 << SAMR_V_SAMSKEACT3
+#define SAMR_M_SAMSKEACT3 (1 << SAMR_V_SAMSKEACT3)
/*
**
@@ -1535,35 +1535,35 @@
#define PMC_AASR_REG 0x01A
#define PMC_AASR_INIT 0x0000
#define AASR_V_WAKE0ACTV 0
-#define AASR_M_WAKE0ACTV 1 << AASR_V_WAKE0ACTV
+#define AASR_M_WAKE0ACTV (1 << AASR_V_WAKE0ACTV)
#define AASR_V_WAKE1ACTV 1
-#define AASR_M_WAKE1ACTV 1 << AASR_V_WAKE1ACTV
+#define AASR_M_WAKE1ACTV (1 << AASR_V_WAKE1ACTV)
#define AASR_V_INTRACTV 2
-#define AASR_M_INTRACTV 1 << AASR_V_INTRACTV
+#define AASR_M_INTRACTV (1 << AASR_V_INTRACTV)
#define AASR_V_DZTO 4
-#define AASR_M_DZTO 1 << AASR_V_DZTO
+#define AASR_M_DZTO (1 << AASR_V_DZTO)
#define AASR_V_SLPTO 5
-#define AASR_M_SLPTO 1 << AASR_V_SLPTO
+#define AASR_M_SLPTO (1 << AASR_V_SLPTO)
#define AASR_V_SPNDTO 6
-#define AASR_M_SPNDTO 1 << AASR_V_SPNDTO
+#define AASR_M_SPNDTO (1 << AASR_V_SPNDTO)
#define AASR_V_GENTO 7
-#define AASR_M_GENTO 1 << AASR_V_GENTO
+#define AASR_M_GENTO (1 << AASR_V_GENTO)
#define AASR_V_PRTMR0TO 8
-#define AASR_M_PRTMR0TO 1 << AASR_V_PRTMR0TO
+#define AASR_M_PRTMR0TO (1 << AASR_V_PRTMR0TO)
#define AASR_V_PRTMR1TO 9
-#define AASR_M_PRTMR1TO 1 << AASR_V_PRTMR0T1
+#define AASR_M_PRTMR1TO (1 << AASR_V_PRTMR0T1)
#define AASR_V_PRTMR2TO 10
-#define AASR_M_PRTMR2TO 1 << AASR_V_PRTMR0T2
+#define AASR_M_PRTMR2TO (1 << AASR_V_PRTMR0T2)
#define AASR_V_PRTMR3TO 11
-#define AASR_M_PRTMR3TO 1 << AASR_V_PRTMR0T3
+#define AASR_M_PRTMR3TO (1 << AASR_V_PRTMR0T3)
#define AASR_V_PRTOPMI0 12
-#define AASR_M_PRTOPMI0 1 << AASR_V_PRTOPMI0
+#define AASR_M_PRTOPMI0 (1 << AASR_V_PRTOPMI0)
#define AASR_V_PRTOPMI1 13
-#define AASR_M_PRTOPMI1 1 << AASR_V_PRTOPMI1
+#define AASR_M_PRTOPMI1 (1 << AASR_V_PRTOPMI1)
#define AASR_V_PRTOPMI2 14
-#define AASR_M_PRTOPMI2 1 << AASR_V_PRTOPMI2
+#define AASR_M_PRTOPMI2 (1 << AASR_V_PRTOPMI2)
#define AASR_V_PRTOPMI3 15
-#define AASR_M_PRTOPMI3 1 << AASR_V_PRTOPMI3
+#define AASR_M_PRTOPMI3 (1 << AASR_V_PRTOPMI3)
/*
**
@@ -1593,27 +1593,27 @@
APAMR_M_PAMSKDMA | APAMR_M_PAMSKMSTR | \
APAMR_M_LMTPACTV )
#define APAMR_V_PAMSKWAKE0 0
-#define APAMR_M_PAMSKWAKE0 1 << APAMR_V_PAMSKWAKE0
+#define APAMR_M_PAMSKWAKE0 (1 << APAMR_V_PAMSKWAKE0)
#define APAMR_V_PAMSKWAKE1 1
-#define APAMR_M_PAMSKWAKE1 1 << APAMR_V_PAMSKWAKE1
+#define APAMR_M_PAMSKWAKE1 (1 << APAMR_V_PAMSKWAKE1)
#define APAMR_V_PAMSKINTR 2
-#define APAMR_M_PAMSKINTR 1 << APAMR_V_PAMSKINTR
+#define APAMR_M_PAMSKINTR (1 << APAMR_V_PAMSKINTR)
#define APAMR_V_PAMSKPMI 3
-#define APAMR_M_PAMSKPMI 1 << APAMR_V_PAMSKPMI
+#define APAMR_M_PAMSKPMI (1 << APAMR_V_PAMSKPMI)
#define APAMR_V_PAMSKHOLD 4
-#define APAMR_M_PAMSKHOLD 1 << APAMR_V_PAMSKHOLD
+#define APAMR_M_PAMSKHOLD (1 << APAMR_V_PAMSKHOLD)
#define APAMR_V_PAMSKNMI 5
-#define APAMR_M_PAMSKNMI 1 << APAMR_V_PAMSKNMI
+#define APAMR_M_PAMSKNMI (1 << APAMR_V_PAMSKNMI)
#define APAMR_V_PAMSKDMA 6
-#define APAMR_M_PAMSKDMA 1 << APAMR_V_PAMSKDMA
+#define APAMR_M_PAMSKDMA (1 << APAMR_V_PAMSKDMA)
#define APAMR_V_PAMSKMSTR 7
-#define APAMR_M_PAMSKMSTR 1 << APAMR_V_PAMSKMSTR
+#define APAMR_M_PAMSKMSTR (1 << APAMR_V_PAMSKMSTR)
#define APAMR_V_DISPACTVON 11
-#define APAMR_M_DISPACTVON 1 << APAMR_V_DISPACTVON
+#define APAMR_M_DISPACTVON (1 << APAMR_V_DISPACTVON)
#define APAMR_V_HD2EN 14
-#define APAMR_M_HD2EN 1 << APAMR_V_HD2EN
+#define APAMR_M_HD2EN (1 << APAMR_V_HD2EN)
#define APAMR_V_LMTPACTV 15
-#define APAMR_M_LMTPACTV 1 << APAMR_V_LMTPACTV
+#define APAMR_M_LMTPACTV (1 << APAMR_V_LMTPACTV)
/*
**
@@ -1643,29 +1643,29 @@
ASCR_M_SAMSKMSTR | ASCR_M_SACTVTMR2 | \
ASCR_M_LMTSACTV )
#define ASCR_V_SAMSKWAKE0 0
-#define ASCR_M_SAMSKWAKE0 1 << ASCR_V_SAMSKWAKE0
+#define ASCR_M_SAMSKWAKE0 (1 << ASCR_V_SAMSKWAKE0)
#define ASCR_V_SAMSKWAKE1 1
-#define ASCR_M_SAMSKWAKE1 1 << ASCR_V_SAMSKWAKE1
+#define ASCR_M_SAMSKWAKE1 (1 << ASCR_V_SAMSKWAKE1)
#define ASCR_V_SAMSKINTR 2
-#define ASCR_M_SAMSKINTR 1 << ASCR_V_SAMSKINTR
+#define ASCR_M_SAMSKINTR (1 << ASCR_V_SAMSKINTR)
#define ASCR_V_SAMSKPMI 3
-#define ASCR_M_SAMSKPMI 1 << ASCR_V_SAMSKPMI
+#define ASCR_M_SAMSKPMI (1 << ASCR_V_SAMSKPMI)
#define ASCR_V_SAMSKIRQ0 4
-#define ASCR_M_SAMSKIRQ0 1 << ASCR_V_SAMSKIRQ0
+#define ASCR_M_SAMSKIRQ0 (1 << ASCR_V_SAMSKIRQ0)
#define ASCR_V_SAMSKDMA 6
-#define ASCR_M_SAMSKDMA 1 << ASCR_V_SAMSKDMA
+#define ASCR_M_SAMSKDMA (1 << ASCR_V_SAMSKDMA)
#define ASCR_V_SAMSKMSTR 7
-#define ASCR_M_SAMSKMSTR 1 << ASCR_V_SAMSKMSTR
+#define ASCR_M_SAMSKMSTR (1 << ASCR_V_SAMSKMSTR)
#define ASCR_V_SACTVTMR 9
-#define ASCR_M_SACTVTMR 0x7 << ASCR_V_SACTVTMR
+#define ASCR_M_SACTVTMR (0x7 << ASCR_V_SACTVTMR)
#define ASCR_V_SACTVTMR0 9
-#define ASCR_M_SACTVTMR0 1 << ASCR_V_SACTVTMR0
+#define ASCR_M_SACTVTMR0 (1 << ASCR_V_SACTVTMR0)
#define ASCR_V_SACTVTMR1 10
-#define ASCR_M_SACTVTMR1 1 << ASCR_V_SACTVTMR1
+#define ASCR_M_SACTVTMR1 (1 << ASCR_V_SACTVTMR1)
#define ASCR_V_SACTVTMR2 11
-#define ASCR_M_SACTVTMR2 1 << ASCR_V_SACTVTMR2
+#define ASCR_M_SACTVTMR2 (1 << ASCR_V_SACTVTMR2)
#define ASCR_V_LMTSACTV 15
-#define ASCR_M_LMTSACTV 1 << ASCR_V_LMTSACTV
+#define ASCR_M_LMTSACTV (1 << ASCR_V_LMTSACTV)
/*
** Secondary Activity Timer
@@ -1706,27 +1706,27 @@
APMIMR_M_IMSKPRTMR2TO | \
APMIMR_M_IMSKPRTMR3TO )
#define APMIMR_V_IMSKWAKE0 0
-#define APMIMR_M_IMSKWAKE0 1 << APMIMR_V_IMSKWAKE0
+#define APMIMR_M_IMSKWAKE0 (1 << APMIMR_V_IMSKWAKE0)
#define APMIMR_V_IMSKWAKE1 1
-#define APMIMR_M_IMSKWAKE1 1 << APMIMR_V_IMSKWAKE1
+#define APMIMR_M_IMSKWAKE1 (1 << APMIMR_V_IMSKWAKE1)
#define APMIMR_V_IMSKRTC 3
-#define APMIMR_M_IMSKRTC 1 << APMIMR_V_IMSKRTC
+#define APMIMR_M_IMSKRTC (1 << APMIMR_V_IMSKRTC)
#define APMIMR_V_RESCHED 4
-#define APMIMR_M_RESCHED 0x3 << APMIMR_V_RESCHED
+#define APMIMR_M_RESCHED (0x3 << APMIMR_V_RESCHED)
#define APMIMR_V_RESCHED0 4
-#define APMIMR_M_RESCHED0 1 << APMIMR_V_RESCHED0
+#define APMIMR_M_RESCHED0 (1 << APMIMR_V_RESCHED0)
#define APMIMR_V_RESCHED1 5
-#define APMIMR_M_RESCHED1 1 << APMIMR_V_RESCHED1
+#define APMIMR_M_RESCHED1 (1 << APMIMR_V_RESCHED1)
#define APMIMR_V_SFTSMI 6
-#define APMIMR_M_SFTSMI 1 << APMIMR_V_SFTSMI
+#define APMIMR_M_SFTSMI (1 << APMIMR_V_SFTSMI)
#define APMIMR_V_IMSKPRTMR0TO 8
-#define APMIMR_M_IMSKPRTMR0TO 1 << APMIMR_V_IMSKPRTMR0TO
+#define APMIMR_M_IMSKPRTMR0TO (1 << APMIMR_V_IMSKPRTMR0TO)
#define APMIMR_V_IMSKPRTMR1TO 9
-#define APMIMR_M_IMSKPRTMR1TO 1 << APMIMR_V_IMSKPRTMR1TO
+#define APMIMR_M_IMSKPRTMR1TO (1 << APMIMR_V_IMSKPRTMR1TO)
#define APMIMR_V_IMSKPRTMR2TO 10
-#define APMIMR_M_IMSKPRTMR2TO 1 << APMIMR_V_IMSKPRTMR2TO
+#define APMIMR_M_IMSKPRTMR2TO (1 << APMIMR_V_IMSKPRTMR2TO)
#define APMIMR_V_IMSKPRTMR3TO 11
-#define APMIMR_M_IMSKPRTMR3TO 1 << APMIMR_V_IMSKPRTMR3TO
+#define APMIMR_M_IMSKPRTMR3TO (1 << APMIMR_V_IMSKPRTMR3TO)
/*
** Reschedule PMI
@@ -1752,11 +1752,11 @@
#define PMC_MCR_REG 0x01E
#define PMC_MCR_INIT 0x0000
#define MCR_V_PMIFLGEN 0
-#define MCR_M_PMIFLGEN 1 << MCR_V_PMIFLGEN
+#define MCR_M_PMIFLGEN (1 << MCR_V_PMIFLGEN)
#define MCR_V_PAFLGEN 1
-#define MCR_M_PAFLGEN 1 << MCR_V_PAFLGEN
+#define MCR_M_PAFLGEN (1 << MCR_V_PAFLGEN)
#define MCR_V_SAFLGEN 2
-#define MCR_M_SAFLGEN 1 << MCR_V_SAFLGEN
+#define MCR_M_SAFLGEN (1 << MCR_V_SAFLGEN)
/*
**
@@ -1774,7 +1774,7 @@
*/
#define PMC_SEQIDR_REG 0x01F
#define SEQIDR_V_SQ1ID 0
-#define SEQIDR_M_SQ1ID 0xF << SEQIDR_V_SQ1ID
+#define SEQIDR_M_SQ1ID (0xF << SEQIDR_V_SQ1ID)
/*
**
@@ -1792,11 +1792,11 @@
#define PMC_PRAR0_REG 0x020
#define PMC_PRAR0_INIT 0x0000
#define PRAR0_V_PRMA 0
-#define PRAR0_M_PRMA 0x3FF << PRAR0_V_PRMA
+#define PRAR0_M_PRMA (0x3FF << PRAR0_V_PRMA)
#define PRAR0_V_PROSHDW0EN 14
-#define PRAR0_M_PROSHDW0EN 1 << PRAR0_V_PROSHDW0EN
+#define PRAR0_M_PROSHDW0EN (1 << PRAR0_V_PROSHDW0EN)
#define PRAR0_V_PROCS0EN 15
-#define PRAR0_M_PROCS0EN 1 << PRAR0_V_PROCS0EN
+#define PRAR0_M_PROCS0EN (1 << PRAR0_V_PROCS0EN)
/*
**
@@ -1825,35 +1825,35 @@
#define PMC_PRCR0_REG 0x021
#define PMC_PRCR0_INIT 0x0000
#define PRCR0_V_PRMCMPEN 0
-#define PRCR0_M_PRMCMPEN 0x3FF << PRCR0_V_PRMCMPEN
+#define PRCR0_M_PRMCMPEN (0x3FF << PRCR0_V_PRMCMPEN)
#define PRCR0_V_PRMCMPEN00 0
-#define PRCR0_M_PRMCMPEN00 1 << PRCR0_V_PRMCMPEN00
+#define PRCR0_M_PRMCMPEN00 (1 << PRCR0_V_PRMCMPEN00)
#define PRCR0_V_PRMCMPEN01 1
-#define PRCR0_M_PRMCMPEN01 1 << PRCR0_V_PRMCMPEN01
+#define PRCR0_M_PRMCMPEN01 (1 << PRCR0_V_PRMCMPEN01)
#define PRCR0_V_PRMCMPEN02 2
-#define PRCR0_M_PRMCMPEN02 1 << PRCR0_V_PRMCMPEN02
+#define PRCR0_M_PRMCMPEN02 (1 << PRCR0_V_PRMCMPEN02)
#define PRCR0_V_PRMCMPEN03 3
-#define PRCR0_M_PRMCMPEN03 1 << PRCR0_V_PRMCMPEN03
+#define PRCR0_M_PRMCMPEN03 (1 << PRCR0_V_PRMCMPEN03)
#define PRCR0_V_PRMCMPEN04 4
-#define PRCR0_M_PRMCMPEN04 1 << PRCR0_V_PRMCMPEN04
+#define PRCR0_M_PRMCMPEN04 (1 << PRCR0_V_PRMCMPEN04)
#define PRCR0_V_PRMCMPEN05 5
-#define PRCR0_M_PRMCMPEN05 1 << PRCR0_V_PRMCMPEN05
+#define PRCR0_M_PRMCMPEN05 (1 << PRCR0_V_PRMCMPEN05)
#define PRCR0_V_PRMCMPEN06 6
-#define PRCR0_M_PRMCMPEN06 1 << PRCR0_V_PRMCMPEN06
+#define PRCR0_M_PRMCMPEN06 (1 << PRCR0_V_PRMCMPEN06)
#define PRCR0_V_PRMCMPEN07 7
-#define PRCR0_M_PRMCMPEN07 1 << PRCR0_V_PRMCMPEN07
+#define PRCR0_M_PRMCMPEN07 (1 << PRCR0_V_PRMCMPEN07)
#define PRCR0_V_PRMCMPEN08 8
-#define PRCR0_M_PRMCMPEN08 1 << PRCR0_V_PRMCMPEN08
+#define PRCR0_M_PRMCMPEN08 (1 << PRCR0_V_PRMCMPEN08)
#define PRCR0_V_PRMCMPEN09 9
-#define PRCR0_M_PRMCMPEN09 1 << PRCR0_V_PRMCMPEN09
+#define PRCR0_M_PRMCMPEN09 (1 << PRCR0_V_PRMCMPEN09)
#define PRCR0_V_PRMWR0EN 10
-#define PRCR0_M_PRMWR0EN 1 << PRCR0_V_PRMWR0EN
+#define PRCR0_M_PRMWR0EN (1 << PRCR0_V_PRMWR0EN)
#define PRCR0_V_PRMRD0EN 11
-#define PRCR0_M_PRMRD0EN 1 << PRCR0_V_PRMRD0EN
+#define PRCR0_M_PRMRD0EN (1 << PRCR0_V_PRMRD0EN)
#define PRCR0_V_PRM0MIO 12
-#define PRCR0_M_PRM0MIO 1 << PRCR0_V_PRM0MIO
+#define PRCR0_M_PRM0MIO (1 << PRCR0_V_PRM0MIO)
#define PRCR0_V_PRM0EN 13
-#define PRCR0_M_PRM0EN 1 << PRCR0_V_PRM0EN
+#define PRCR0_M_PRM0EN (1 << PRCR0_V_PRM0EN)
/*
**
@@ -1870,11 +1870,11 @@
*/
#define PMC_PRAR1_REG 0x022
#define PRAR1_V_PRMA 0
-#define PRAR1_M_PRMA 0x3FF << PRAR1_V_PRMA
+#define PRAR1_M_PRMA (0x3FF << PRAR1_V_PRMA)
#define PRAR1_V_PROSHDW1EN 14
-#define PRAR1_M_PROSHDW1EN 1 << PRAR1_V_PROSHDW1EN
+#define PRAR1_M_PROSHDW1EN (1 << PRAR1_V_PROSHDW1EN)
#define PRAR1_V_PROCS1EN 15
-#define PRAR1_M_PROCS1EN 1 << PRAR1_V_PROCS1EN
+#define PRAR1_M_PROCS1EN (1 << PRAR1_V_PROCS1EN)
/*
**
@@ -1903,35 +1903,35 @@
#define PMC_PRCR1_REG 0x023
#define PMC_PRCR1_INIT 0x0000
#define PRCR1_V_PRMCMPEN 0
-#define PRCR1_M_PRMCMPEN 0x3FF << PRCR1_V_PRMCMPEN
+#define PRCR1_M_PRMCMPEN (0x3FF << PRCR1_V_PRMCMPEN)
#define PRCR1_V_PRMCMPEN10 0
-#define PRCR1_M_PRMCMPEN10 1 << PRCR1_V_PRMCMPEN10
+#define PRCR1_M_PRMCMPEN10 (1 << PRCR1_V_PRMCMPEN10)
#define PRCR1_V_PRMCMPEN11 1
-#define PRCR1_M_PRMCMPEN11 1 << PRCR1_V_PRMCMPEN11
+#define PRCR1_M_PRMCMPEN11 (1 << PRCR1_V_PRMCMPEN11)
#define PRCR1_V_PRMCMPEN12 2
-#define PRCR1_M_PRMCMPEN12 1 << PRCR1_V_PRMCMPEN12
+#define PRCR1_M_PRMCMPEN12 (1 << PRCR1_V_PRMCMPEN12)
#define PRCR1_V_PRMCMPEN13 3
-#define PRCR1_M_PRMCMPEN13 1 << PRCR1_V_PRMCMPEN13
+#define PRCR1_M_PRMCMPEN13 (1 << PRCR1_V_PRMCMPEN13)
#define PRCR1_V_PRMCMPEN14 4
-#define PRCR1_M_PRMCMPEN14 1 << PRCR1_V_PRMCMPEN14
+#define PRCR1_M_PRMCMPEN14 (1 << PRCR1_V_PRMCMPEN14)
#define PRCR1_V_PRMCMPEN15 5
-#define PRCR1_M_PRMCMPEN15 1 << PRCR1_V_PRMCMPEN15
+#define PRCR1_M_PRMCMPEN15 (1 << PRCR1_V_PRMCMPEN15)
#define PRCR1_V_PRMCMPEN16 6
-#define PRCR1_M_PRMCMPEN16 1 << PRCR1_V_PRMCMPEN16
+#define PRCR1_M_PRMCMPEN16 (1 << PRCR1_V_PRMCMPEN16)
#define PRCR1_V_PRMCMPEN17 7
-#define PRCR1_M_PRMCMPEN17 1 << PRCR1_V_PRMCMPEN17
+#define PRCR1_M_PRMCMPEN17 (1 << PRCR1_V_PRMCMPEN17)
#define PRCR1_V_PRMCMPEN18 8
-#define PRCR1_M_PRMCMPEN18 1 << PRCR1_V_PRMCMPEN18
+#define PRCR1_M_PRMCMPEN18 (1 << PRCR1_V_PRMCMPEN18)
#define PRCR1_V_PRMCMPEN19 9
-#define PRCR1_M_PRMCMPEN19 1 << PRCR1_V_PRMCMPEN19
+#define PRCR1_M_PRMCMPEN19 (1 << PRCR1_V_PRMCMPEN19)
#define PRCR1_V_PRMWR1EN 10
-#define PRCR1_M_PRMWR1EN 1 << PRCR1_V_PRMWR1EN
+#define PRCR1_M_PRMWR1EN (1 << PRCR1_V_PRMWR1EN)
#define PRCR1_V_PRMRD1EN 11
-#define PRCR1_M_PRMRD1EN 1 << PRCR1_V_PRMRD1EN
+#define PRCR1_M_PRMRD1EN (1 << PRCR1_V_PRMRD1EN)
#define PRCR1_V_PRM1MIO 12
-#define PRCR1_M_PRM1MIO 1 << PRCR1_V_PRM1MIO
+#define PRCR1_M_PRM1MIO (1 << PRCR1_V_PRM1MIO)
#define PRCR1_V_PRM1EN 13
-#define PRCR1_M_PRM1EN 1 << PRCR1_V_PRM1EN
+#define PRCR1_M_PRM1EN (1 << PRCR1_V_PRM1EN)
/*
**
@@ -1948,11 +1948,11 @@
*/
#define PMC_PRAR2_REG 0x024
#define PRAR2_V_PRMA 0
-#define PRAR2_M_PRMA 0x3FF << PRAR2_V_PRMA
+#define PRAR2_M_PRMA (0x3FF << PRAR2_V_PRMA)
#define PRAR2_V_PROSHDW2EN 14
-#define PRAR2_M_PROSHDW2EN 1 << PRAR2_V_PROSHDW2EN
+#define PRAR2_M_PROSHDW2EN (1 << PRAR2_V_PROSHDW2EN)
#define PRAR2_V_PROCS2EN 15
-#define PRAR2_M_PROCS2EN 1 << PRAR2_V_PROCS2EN
+#define PRAR2_M_PROCS2EN (1 << PRAR2_V_PROCS2EN)
/*
**
@@ -1981,35 +1981,35 @@
#define PMC_PRCR2_REG 0x025
#define PMC_PRCR2_INIT 0x0000
#define PRCR2_V_PRMCMPEN 0
-#define PRCR2_M_PRMCMPEN 0x3FF << PRCR2_V_PRMCMPEN
+#define PRCR2_M_PRMCMPEN (0x3FF << PRCR2_V_PRMCMPEN)
#define PRCR2_V_PRMCMPEN10 0
-#define PRCR2_M_PRMCMPEN10 1 << PRCR2_V_PRMCMPEN10
+#define PRCR2_M_PRMCMPEN10 (1 << PRCR2_V_PRMCMPEN10)
#define PRCR2_V_PRMCMPEN11 1
-#define PRCR2_M_PRMCMPEN11 1 << PRCR2_V_PRMCMPEN11
+#define PRCR2_M_PRMCMPEN11 (1 << PRCR2_V_PRMCMPEN11)
#define PRCR2_V_PRMCMPEN12 2
-#define PRCR2_M_PRMCMPEN12 1 << PRCR2_V_PRMCMPEN12
+#define PRCR2_M_PRMCMPEN12 (1 << PRCR2_V_PRMCMPEN12)
#define PRCR2_V_PRMCMPEN13 3
-#define PRCR2_M_PRMCMPEN13 1 << PRCR2_V_PRMCMPEN13
+#define PRCR2_M_PRMCMPEN13 (1 << PRCR2_V_PRMCMPEN13)
#define PRCR2_V_PRMCMPEN14 4
-#define PRCR2_M_PRMCMPEN14 1 << PRCR2_V_PRMCMPEN14
+#define PRCR2_M_PRMCMPEN14 (1 << PRCR2_V_PRMCMPEN14)
#define PRCR2_V_PRMCMPEN15 5
-#define PRCR2_M_PRMCMPEN15 1 << PRCR2_V_PRMCMPEN15
+#define PRCR2_M_PRMCMPEN15 (1 << PRCR2_V_PRMCMPEN15)
#define PRCR2_V_PRMCMPEN16 6
-#define PRCR2_M_PRMCMPEN16 1 << PRCR2_V_PRMCMPEN16
+#define PRCR2_M_PRMCMPEN16 (1 << PRCR2_V_PRMCMPEN16)
#define PRCR2_V_PRMCMPEN17 7
-#define PRCR2_M_PRMCMPEN17 1 << PRCR2_V_PRMCMPEN17
+#define PRCR2_M_PRMCMPEN17 (1 << PRCR2_V_PRMCMPEN17)
#define PRCR2_V_PRMCMPEN18 8
-#define PRCR2_M_PRMCMPEN18 1 << PRCR2_V_PRMCMPEN18
+#define PRCR2_M_PRMCMPEN18 (1 << PRCR2_V_PRMCMPEN18)
#define PRCR2_V_PRMCMPEN19 9
-#define PRCR2_M_PRMCMPEN19 1 << PRCR2_V_PRMCMPEN19
+#define PRCR2_M_PRMCMPEN19 (1 << PRCR2_V_PRMCMPEN19)
#define PRCR2_V_PRMWR2EN 10
-#define PRCR2_M_PRMWR2EN 1 << PRCR2_V_PRMWR2EN
+#define PRCR2_M_PRMWR2EN (1 << PRCR2_V_PRMWR2EN)
#define PRCR2_V_PRMRD2EN 11
-#define PRCR2_M_PRMRD2EN 1 << PRCR2_V_PRMRD2EN
+#define PRCR2_M_PRMRD2EN (1 << PRCR2_V_PRMRD2EN)
#define PRCR2_V_PRM2MIO 12
-#define PRCR2_M_PRM2MIO 1 << PRCR2_V_PRM2MIO
+#define PRCR2_M_PRM2MIO (1 << PRCR2_V_PRM2MIO)
#define PRCR2_V_PRM2EN 13
-#define PRCR2_M_PRM2EN 1 << PRCR2_V_PRM2EN
+#define PRCR2_M_PRM2EN (1 << PRCR2_V_PRM2EN)
/*
**
@@ -2027,11 +2027,11 @@
#define PMC_PRAR3_REG 0x026
#define PMC_PRAR3_INIT 0x0000
#define PRAR3_V_PRMA 0
-#define PRAR3_M_PRMA 0x3FF << PRAR3_V_PRMA
+#define PRAR3_M_PRMA (0x3FF << PRAR3_V_PRMA)
#define PRAR3_V_PROSHDW3EN 14
-#define PRAR3_M_PROSHDW3EN 1 << PRAR3_V_PROSHDW3EN
+#define PRAR3_M_PROSHDW3EN (1 << PRAR3_V_PROSHDW3EN)
#define PRAR3_V_PROCS3EN 15
-#define PRAR3_M_PROCS3EN 1 << PRAR3_V_PROCS3EN
+#define PRAR3_M_PROCS3EN (1 << PRAR3_V_PROCS3EN)
/*
**
@@ -2060,35 +2060,35 @@
#define PMC_PRCR3_REG 0x027
#define PMC_PRCR3_INIT 0x0000
#define PRCR3_V_PRMCMPEN 0
-#define PRCR3_M_PRMCMPEN 0x3FF << PRCR3_V_PRMCMPEN
+#define PRCR3_M_PRMCMPEN (0x3FF << PRCR3_V_PRMCMPEN)
#define PRCR3_V_PRMCMPEN10 0
-#define PRCR3_M_PRMCMPEN10 1 << PRCR3_V_PRMCMPEN10
+#define PRCR3_M_PRMCMPEN10 (1 << PRCR3_V_PRMCMPEN10)
#define PRCR3_V_PRMCMPEN11 1
-#define PRCR3_M_PRMCMPEN11 1 << PRCR3_V_PRMCMPEN11
+#define PRCR3_M_PRMCMPEN11 (1 << PRCR3_V_PRMCMPEN11)
#define PRCR3_V_PRMCMPEN12 2
-#define PRCR3_M_PRMCMPEN12 1 << PRCR3_V_PRMCMPEN12
+#define PRCR3_M_PRMCMPEN12 (1 << PRCR3_V_PRMCMPEN12)
#define PRCR3_V_PRMCMPEN13 3
-#define PRCR3_M_PRMCMPEN13 1 << PRCR3_V_PRMCMPEN13
+#define PRCR3_M_PRMCMPEN13 (1 << PRCR3_V_PRMCMPEN13)
#define PRCR3_V_PRMCMPEN14 4
-#define PRCR3_M_PRMCMPEN14 1 << PRCR3_V_PRMCMPEN14
+#define PRCR3_M_PRMCMPEN14 (1 << PRCR3_V_PRMCMPEN14)
#define PRCR3_V_PRMCMPEN15 5
-#define PRCR3_M_PRMCMPEN15 1 << PRCR3_V_PRMCMPEN15
+#define PRCR3_M_PRMCMPEN15 (1 << PRCR3_V_PRMCMPEN15)
#define PRCR3_V_PRMCMPEN16 6
-#define PRCR3_M_PRMCMPEN16 1 << PRCR3_V_PRMCMPEN16
+#define PRCR3_M_PRMCMPEN16 (1 << PRCR3_V_PRMCMPEN16)
#define PRCR3_V_PRMCMPEN17 7
-#define PRCR3_M_PRMCMPEN17 1 << PRCR3_V_PRMCMPEN17
+#define PRCR3_M_PRMCMPEN17 (1 << PRCR3_V_PRMCMPEN17)
#define PRCR3_V_PRMCMPEN18 8
-#define PRCR3_M_PRMCMPEN18 1 << PRCR3_V_PRMCMPEN18
+#define PRCR3_M_PRMCMPEN18 (1 << PRCR3_V_PRMCMPEN18)
#define PRCR3_V_PRMCMPEN19 9
-#define PRCR3_M_PRMCMPEN19 1 << PRCR3_V_PRMCMPEN19
+#define PRCR3_M_PRMCMPEN19 (1 << PRCR3_V_PRMCMPEN19)
#define PRCR3_V_PRMWR3EN 10
-#define PRCR3_M_PRMWR3EN 1 << PRCR3_V_PRMWR3EN
+#define PRCR3_M_PRMWR3EN (1 << PRCR3_V_PRMWR3EN)
#define PRCR3_V_PRMRD3EN 11
-#define PRCR3_M_PRMRD3EN 1 << PRCR3_V_PRMRD3EN
+#define PRCR3_M_PRMRD3EN (1 << PRCR3_V_PRMRD3EN)
#define PRCR3_V_PRM3MIO 12
-#define PRCR3_M_PRM3MIO 1 << PRCR3_V_PRM3MIO
+#define PRCR3_M_PRM3MIO (1 << PRCR3_V_PRM3MIO)
#define PRCR3_V_PRM3EN 13
-#define PRCR3_M_PRM3EN 1 << PRCR3_V_PRM3EN
+#define PRCR3_M_PRM3EN (1 << PRCR3_V_PRM3EN)
/*
**
@@ -2110,21 +2110,21 @@
#define PMC_PTOTR0_REG 0x028
#define PMC_PTOTR0_INIT 0x0000
#define PTOTR0_V_PROGTMR0 0
-#define PTOTR0_M_PROGTMR0 0xF << PTOTR0_V_PROGTMR0
+#define PTOTR0_M_PROGTMR0 (0xF << PTOTR0_V_PROGTMR0)
#define PTOTR0_V_PROGTMR00 0
-#define PTOTR0_M_PROGTMR00 1 << PTOTR0_V_PROGTMR00
+#define PTOTR0_M_PROGTMR00 (1 << PTOTR0_V_PROGTMR00)
#define PTOTR0_V_PROGTMR01 1
-#define PTOTR0_M_PROGTMR01 1 << PTOTR0_V_PROGTMR01
+#define PTOTR0_M_PROGTMR01 (1 << PTOTR0_V_PROGTMR01)
#define PTOTR0_V_PROGTMR02 2
-#define PTOTR0_M_PROGTMR02 1 << PTOTR0_V_PROGTMR02
+#define PTOTR0_M_PROGTMR02 (1 << PTOTR0_V_PROGTMR02)
#define PTOTR0_V_PROGTMR03 3
-#define PTOTR0_M_PROGTMR03 1 << PTOTR0_V_PROGTMR03
+#define PTOTR0_M_PROGTMR03 (1 << PTOTR0_V_PROGTMR03)
#define PTOTR0_V_TMR0SOURCE 7
-#define PTOTR0_M_TMR0SOURCE 1 << PTOTR0_V_TMR0SOURCE
+#define PTOTR0_M_TMR0SOURCE (1 << PTOTR0_V_TMR0SOURCE)
#define PTOTR0_V_TMR0PC2EN 14
-#define PTOTR0_M_TMR0PC2EN 1 << PTOTR0_V_TMR0PC2EN
+#define PTOTR0_M_TMR0PC2EN (1 << PTOTR0_V_TMR0PC2EN)
#define PTOTR0_V_TMR0EN 15
-#define PTOTR0_M_TMR0EN 1 << PTOTR0_V_TMR0EN
+#define PTOTR0_M_TMR0EN (1 << PTOTR0_V_TMR0EN)
/*
** Progammable Time-out Timer 0
@@ -2166,21 +2166,21 @@
#define PMC_PTOTR1_REG 0x029
#define PMC_PTOTR1_INIT 0x0000
#define PTOTR1_V_PROGTMR1 0
-#define PTOTR1_M_PROGTMR1 0xF << PTOTR1_V_PROGTMR1
+#define PTOTR1_M_PROGTMR1 (0xF << PTOTR1_V_PROGTMR1)
#define PTOTR1_V_PROGTMR10 0
-#define PTOTR1_M_PROGTMR10 1 << PTOTR1_V_PROGTMR10
+#define PTOTR1_M_PROGTMR10 (1 << PTOTR1_V_PROGTMR10)
#define PTOTR1_V_PROGTMR11 1
-#define PTOTR1_M_PROGTMR11 1 << PTOTR1_V_PROGTMR11
+#define PTOTR1_M_PROGTMR11 (1 << PTOTR1_V_PROGTMR11)
#define PTOTR1_V_PROGTMR12 2
-#define PTOTR1_M_PROGTMR12 1 << PTOTR1_V_PROGTMR12
+#define PTOTR1_M_PROGTMR12 (1 << PTOTR1_V_PROGTMR12)
#define PTOTR1_V_PROGTMR13 3
-#define PTOTR1_M_PROGTMR13 1 << PTOTR1_V_PROGTMR13
+#define PTOTR1_M_PROGTMR13 (1 << PTOTR1_V_PROGTMR13)
#define PTOTR1_V_TMR1SOURCE 7
-#define PTOTR1_M_TMR1SOURCE 1 << PTOTR1_V_TMR1SOURCE
+#define PTOTR1_M_TMR1SOURCE (1 << PTOTR1_V_TMR1SOURCE)
#define PTOTR1_V_TMR1PC3EN 14
-#define PTOTR1_M_TMR1PC3EN 1 << PTOTR1_V_TMR1PC3EN
+#define PTOTR1_M_TMR1PC3EN (1 << PTOTR1_V_TMR1PC3EN)
#define PTOTR1_V_TMR1EN 15
-#define PTOTR1_M_TMR1EN 1 << PTOTR1_V_TMR1EN
+#define PTOTR1_M_TMR1EN (1 << PTOTR1_V_TMR1EN)
/*
** Progammable Time-out Timer 1
@@ -2222,21 +2222,21 @@
#define PMC_PTOTR2_REG 0x02A
#define PMC_PTOTR2_INIT 0x0000
#define PTOTR2_V_PROGTMR2 0
-#define PTOTR2_M_PROGTMR2 0xF << PTOTR2_V_PROGTMR2
+#define PTOTR2_M_PROGTMR2 (0xF << PTOTR2_V_PROGTMR2)
#define PTOTR2_V_PROGTMR20 0
-#define PTOTR2_M_PROGTMR20 1 << PTOTR2_V_PROGTMR20
+#define PTOTR2_M_PROGTMR20 (1 << PTOTR2_V_PROGTMR20)
#define PTOTR2_V_PROGTMR21 1
-#define PTOTR2_M_PROGTMR21 1 << PTOTR2_V_PROGTMR21
+#define PTOTR2_M_PROGTMR21 (1 << PTOTR2_V_PROGTMR21)
#define PTOTR2_V_PROGTMR22 2
-#define PTOTR2_M_PROGTMR22 1 << PTOTR2_V_PROGTMR22
+#define PTOTR2_M_PROGTMR22 (1 << PTOTR2_V_PROGTMR22)
#define PTOTR2_V_PROGTMR23 3
-#define PTOTR2_M_PROGTMR23 1 << PTOTR2_V_PROGTMR23
+#define PTOTR2_M_PROGTMR23 (1 << PTOTR2_V_PROGTMR23)
#define PTOTR2_V_TMR2SOURCE 7
-#define PTOTR2_M_TMR2SOURCE 1 << PTOTR2_V_TMR2SOURCE
+#define PTOTR2_M_TMR2SOURCE (1 << PTOTR2_V_TMR2SOURCE)
#define PTOTR2_V_TMR2PC8EN 14
-#define PTOTR2_M_TMR2PC8EN 1 << PTOTR2_V_TMR2PC8EN
+#define PTOTR2_M_TMR2PC8EN (1 << PTOTR2_V_TMR2PC8EN)
#define PTOTR2_V_TMR2EN 15
-#define PTOTR2_M_TMR2EN 1 << PTOTR2_V_TMR2EN
+#define PTOTR2_M_TMR2EN (1 << PTOTR2_V_TMR2EN)
/*
** Progammable Time-out Timer 2
@@ -2278,21 +2278,21 @@
#define PMC_PTOTR3_REG 0x02B
#define PMC_PTOTR3_INIT 0x0000
#define PTOTR3_V_PROGTMR3 0
-#define PTOTR3_M_PROGTMR3 0xF << PTOTR3_V_PROGTMR3
+#define PTOTR3_M_PROGTMR3 (0xF << PTOTR3_V_PROGTMR3)
#define PTOTR3_V_PROGTMR30 0
-#define PTOTR3_M_PROGTMR30 1 << PTOTR3_V_PROGTMR30
+#define PTOTR3_M_PROGTMR30 (1 << PTOTR3_V_PROGTMR30)
#define PTOTR3_V_PROGTMR31 1
-#define PTOTR3_M_PROGTMR31 1 << PTOTR3_V_PROGTMR31
+#define PTOTR3_M_PROGTMR31 (1 << PTOTR3_V_PROGTMR31)
#define PTOTR3_V_PROGTMR32 2
-#define PTOTR3_M_PROGTMR32 1 << PTOTR3_V_PROGTMR32
+#define PTOTR3_M_PROGTMR32 (1 << PTOTR3_V_PROGTMR32)
#define PTOTR3_V_PROGTMR33 3
-#define PTOTR3_M_PROGTMR33 1 << PTOTR3_V_PROGTMR33
+#define PTOTR3_M_PROGTMR33 (1 << PTOTR3_V_PROGTMR33)
#define PTOTR3_V_TMR3SOURCE 7
-#define PTOTR3_M_TMR3SOURCE 1 << PTOTR3_V_TMR3SOURCE
+#define PTOTR3_M_TMR3SOURCE (1 << PTOTR3_V_TMR3SOURCE)
#define PTOTR3_V_TMR3PC9EN 14
-#define PTOTR3_M_TMR3PC9EN 1 << PTOTR3_V_TMR3PC9EN
+#define PTOTR3_M_TMR3PC9EN (1 << PTOTR3_V_TMR3PC9EN)
#define PTOTR3_V_TMR3EN 15
-#define PTOTR3_M_TMR3EN 1 << PTOTR3_V_TMR3EN
+#define PTOTR3_M_TMR3EN (1 << PTOTR3_V_TMR3EN)
/*
** Progammable Time-out Timer 3
@@ -2339,37 +2339,37 @@
#define PMC_PTOTSR1_REG 0x02C
#define PMC_PTOTSR1_INIT 0x0000
#define PTOTSR1_V_VDTMRSEL 0
-#define PTOTSR1_M_VDTMRSEL 0x3 << PTOTSR1_V_VDTMRSEL
+#define PTOTSR1_M_VDTMRSEL (0x3 << PTOTSR1_V_VDTMRSEL)
#define PTOTSR1_V_VDTMRSEL0 0
-#define PTOTSR1_M_VDTMRSEL0 1 << PTOTSR1_V_VDTMRSEL0
+#define PTOTSR1_M_VDTMRSEL0 (1 << PTOTSR1_V_VDTMRSEL0)
#define PTOTSR1_V_VDTMRSEL1 1
-#define PTOTSR1_M_VDTMRSEL1 1 << PTOTSR1_V_VDTMRSEL1
+#define PTOTSR1_M_VDTMRSEL1 (1 << PTOTSR1_V_VDTMRSEL1)
#define PTOTSR1_V_VDTMRSELEN 3
-#define PTOTSR1_M_VDTMRSELEN 1 << PTOTSR1_V_VDTMRSELEN
+#define PTOTSR1_M_VDTMRSELEN (1 << PTOTSR1_V_VDTMRSELEN)
#define PTOTSR1_V_HDTMRSEL 4
-#define PTOTSR1_M_HDTMRSEL 0x3 << PTOTSR1_V_HDTMRSEL
+#define PTOTSR1_M_HDTMRSEL (0x3 << PTOTSR1_V_HDTMRSEL)
#define PTOTSR1_V_HDTMRSEL0 4
-#define PTOTSR1_M_HDTMRSEL0 1 << PTOTSR1_V_HDTMRSEL0
+#define PTOTSR1_M_HDTMRSEL0 (1 << PTOTSR1_V_HDTMRSEL0)
#define PTOTSR1_V_HDTMRSEL1 5
-#define PTOTSR1_M_HDTMRSEL1 1 << PTOTSR1_V_HDTMRSEL1
+#define PTOTSR1_M_HDTMRSEL1 (1 << PTOTSR1_V_HDTMRSEL1)
#define PTOTSR1_V_HDTMRSELEN 7
-#define PTOTSR1_M_HDTMRSELEN 1 << PTOTSR1_V_HDTMRSELEN
+#define PTOTSR1_M_HDTMRSELEN (1 << PTOTSR1_V_HDTMRSELEN)
#define PTOTSR1_V_FDTMRSEL 8
-#define PTOTSR1_M_FDTMRSEL 0x3 << PTOTSR1_V_FDTMRSEL
+#define PTOTSR1_M_FDTMRSEL (0x3 << PTOTSR1_V_FDTMRSEL)
#define PTOTSR1_V_FDTMRSEL0 8
-#define PTOTSR1_M_FDTMRSEL0 1 << PTOTSR1_V_FDTMRSEL0
+#define PTOTSR1_M_FDTMRSEL0 (1 << PTOTSR1_V_FDTMRSEL0)
#define PTOTSR1_V_FDTMRSEL1 9
-#define PTOTSR1_M_FDTMRSEL1 1 << PTOTSR1_V_FDTMRSEL1
+#define PTOTSR1_M_FDTMRSEL1 (1 << PTOTSR1_V_FDTMRSEL1)
#define PTOTSR1_V_FDTMRSELEN 11
-#define PTOTSR1_M_FDTMRSELEN 1 << PTOTSR1_V_FDTMRSELEN
+#define PTOTSR1_M_FDTMRSELEN (1 << PTOTSR1_V_FDTMRSELEN)
#define PTOTSR1_V_KBTMRSEL 12
-#define PTOTSR1_M_KBTMRSEL 0x3 << PTOTSR1_V_KBTMRSEL
+#define PTOTSR1_M_KBTMRSEL (0x3 << PTOTSR1_V_KBTMRSEL)
#define PTOTSR1_V_KBTMRSEL0 12
-#define PTOTSR1_M_KBTMRSEL0 1 << PTOTSR1_V_KBTMRSEL0
+#define PTOTSR1_M_KBTMRSEL0 (1 << PTOTSR1_V_KBTMRSEL0)
#define PTOTSR1_V_KBTMRSEL1 13
-#define PTOTSR1_M_KBTMRSEL1 1 << PTOTSR1_V_KBTMRSEL1
+#define PTOTSR1_M_KBTMRSEL1 (1 << PTOTSR1_V_KBTMRSEL1)
#define PTOTSR1_V_KBTMRSELEN 15
-#define PTOTSR1_M_KBTMRSELEN 1 << PTOTSR1_V_KBTMRSELEN
+#define PTOTSR1_M_KBTMRSELEN (1 << PTOTSR1_V_KBTMRSELEN)
/*
** Video Activity Progammable Time-out Timer
@@ -2428,37 +2428,37 @@
#define PMC_PTOTSR2_REG 0x02D
#define PMC_PTOTSR2_INIT 0x0000
#define PTOTSR2_V_SIOTMRSEL 0
-#define PTOTSR2_M_SIOTMRSEL 0x3 << PTOTSR2_V_SIOTMRSEL
+#define PTOTSR2_M_SIOTMRSEL (0x3 << PTOTSR2_V_SIOTMRSEL)
#define PTOTSR2_V_SIOTMRSEL0 0
-#define PTOTSR2_M_SIOTMRSEL0 1 << PTOTSR2_V_SIOTMRSEL0
+#define PTOTSR2_M_SIOTMRSEL0 (1 << PTOTSR2_V_SIOTMRSEL0)
#define PTOTSR2_V_SIOTMRSEL1 1
-#define PTOTSR2_M_SIOTMRSEL1 1 << PTOTSR2_V_SIOTMRSEL1
+#define PTOTSR2_M_SIOTMRSEL1 (1 << PTOTSR2_V_SIOTMRSEL1)
#define PTOTSR2_V_SIOTMRSELEN 3
-#define PTOTSR2_M_SIOTMRSELEN 1 << PTOTSR2_V_SIOTMRSELEN
+#define PTOTSR2_M_SIOTMRSELEN (1 << PTOTSR2_V_SIOTMRSELEN)
#define PTOTSR2_V_PIOTMRSEL 4
-#define PTOTSR2_M_PIOTMRSEL 0x3 << PTOTSR2_V_PIOTMRSEL
+#define PTOTSR2_M_PIOTMRSEL (0x3 << PTOTSR2_V_PIOTMRSEL)
#define PTOTSR2_V_PIOTMRSEL0 4
-#define PTOTSR2_M_PIOTMRSEL0 1 << PTOTSR2_V_PIOTMRSEL0
+#define PTOTSR2_M_PIOTMRSEL0 (1 << PTOTSR2_V_PIOTMRSEL0)
#define PTOTSR2_V_PIOTMRSEL1 5
-#define PTOTSR2_M_PIOTMRSEL1 1 << PTOTSR2_V_PIOTMRSEL1
+#define PTOTSR2_M_PIOTMRSEL1 (1 << PTOTSR2_V_PIOTMRSEL1)
#define PTOTSR2_V_PIOTMRSELEN 7
-#define PTOTSR2_M_PIOTMRSELEN 1 << PTOTSR2_V_PIOTMRSELEN
+#define PTOTSR2_M_PIOTMRSELEN (1 << PTOTSR2_V_PIOTMRSELEN)
#define PTOTSR2_V_PR0TMRSEL 8
-#define PTOTSR2_M_PR0TMRSEL 0x3 << PTOTSR2_V_PR0TMRSEL
+#define PTOTSR2_M_PR0TMRSEL (0x3 << PTOTSR2_V_PR0TMRSEL)
#define PTOTSR2_V_PR0TMRSEL0 8
-#define PTOTSR2_M_PR0TMRSEL0 1 << PTOTSR2_V_PR0TMRSEL0
+#define PTOTSR2_M_PR0TMRSEL0 (1 << PTOTSR2_V_PR0TMRSEL0)
#define PTOTSR2_V_PR0TMRSEL1 9
-#define PTOTSR2_M_PR0TMRSEL1 1 << PTOTSR2_V_PR0TMRSEL1
+#define PTOTSR2_M_PR0TMRSEL1 (1 << PTOTSR2_V_PR0TMRSEL1)
#define PTOTSR2_V_PR0TMRSELEN 11
-#define PTOTSR2_M_PR0TMRSELEN 1 << PTOTSR2_V_PR0TMRSELEN
+#define PTOTSR2_M_PR0TMRSELEN (1 << PTOTSR2_V_PR0TMRSELEN)
#define PTOTSR2_V_PR1TMRSEL 12
-#define PTOTSR2_M_PR1TMRSEL 0x3 << PTOTSR2_V_PR1TMRSEL
+#define PTOTSR2_M_PR1TMRSEL (0x3 << PTOTSR2_V_PR1TMRSEL)
#define PTOTSR2_V_PR1TMRSEL0 12
-#define PTOTSR2_M_PR1TMRSEL0 1 << PTOTSR2_V_PR1TMRSEL0
+#define PTOTSR2_M_PR1TMRSEL0 (1 << PTOTSR2_V_PR1TMRSEL0)
#define PTOTSR2_V_PR1TMRSEL1 13
-#define PTOTSR2_M_PR1TMRSEL1 1 << PTOTSR2_V_PR1TMRSEL1
+#define PTOTSR2_M_PR1TMRSEL1 (1 << PTOTSR2_V_PR1TMRSEL1)
#define PTOTSR2_V_PR1TMRSELEN 15
-#define PTOTSR2_M_PR1TMRSELEN 1 << PTOTSR2_V_PR1TMRSELEN
+#define PTOTSR2_M_PR1TMRSELEN (1 << PTOTSR2_V_PR1TMRSELEN)
/*
** Serial Port Activity Progammable Time-out Timer
@@ -2511,21 +2511,21 @@
#define PMC_PTOTSR3_REG 0x02E
#define PMC_PTOTSR3_INIT 0x0000
#define PTOTSR3_V_PR2TMRSEL 0
-#define PTOTSR3_M_PR2TMRSEL 0x3 << PTOTSR3_V_PR2TMRSEL
+#define PTOTSR3_M_PR2TMRSEL (0x3 << PTOTSR3_V_PR2TMRSEL)
#define PTOTSR3_V_PR2TMRSEL0 0
-#define PTOTSR3_M_PR2TMRSEL0 1 << PTOTSR3_V_PR2TMRSEL0
+#define PTOTSR3_M_PR2TMRSEL0 (1 << PTOTSR3_V_PR2TMRSEL0)
#define PTOTSR3_V_PR2TMRSEL1 1
-#define PTOTSR3_M_PR2TMRSEL1 1 << PTOTSR3_V_PR2TMRSEL1
+#define PTOTSR3_M_PR2TMRSEL1 (1 << PTOTSR3_V_PR2TMRSEL1)
#define PTOTSR3_V_PR2TMRSELEN 3
-#define PTOTSR3_M_PR2TMRSELEN 1 << PTOTSR3_V_PR2TMRSELEN
+#define PTOTSR3_M_PR2TMRSELEN (1 << PTOTSR3_V_PR2TMRSELEN)
#define PTOTSR3_V_PR3TMRSEL 4
-#define PTOTSR3_M_PR3TMRSEL 0x3 << PTOTSR3_V_PR3TMRSEL
+#define PTOTSR3_M_PR3TMRSEL (0x3 << PTOTSR3_V_PR3TMRSEL)
#define PTOTSR3_V_PR3TMRSEL0 4
-#define PTOTSR3_M_PR3TMRSEL0 1 << PTOTSR3_V_PR3TMRSEL0
+#define PTOTSR3_M_PR3TMRSEL0 (1 << PTOTSR3_V_PR3TMRSEL0)
#define PTOTSR3_V_PR3TMRSEL1 5
-#define PTOTSR3_M_PR3TMRSEL1 1 << PTOTSR3_V_PR3TMRSEL1
+#define PTOTSR3_M_PR3TMRSEL1 (1 << PTOTSR3_V_PR3TMRSEL1)
#define PTOTSR3_V_PR3TMRSELEN 7
-#define PTOTSR3_M_PR3TMRSELEN 1 << PTOTSR3_V_PR3TMRSELEN
+#define PTOTSR3_M_PR3TMRSELEN (1 << PTOTSR3_V_PR3TMRSELEN)
/*
** PRM 2 Activity Progammable Time-out Timer
@@ -2568,37 +2568,37 @@
#define PMC_PTOTSR4_REG 0x02F
#define PMC_PTOTSR4_INIT 0x0000
#define PTOTSR4_V_EXT0TMRSEL 0
-#define PTOTSR4_M_EXT0TMRSEL 0x3 << PTOTSR4_V_EXT0TMRSEL
+#define PTOTSR4_M_EXT0TMRSEL (0x3 << PTOTSR4_V_EXT0TMRSEL)
#define PTOTSR4_V_EXT0TMRSEL0 0
-#define PTOTSR4_M_EXT0TMRSEL0 1 << PTOTSR4_V_EXT0TMRSEL0
+#define PTOTSR4_M_EXT0TMRSEL0 (1 << PTOTSR4_V_EXT0TMRSEL0)
#define PTOTSR4_V_EXT0TMRSEL1 1
-#define PTOTSR4_M_EXT0TMRSEL1 1 << PTOTSR4_V_EXT0TMRSEL1
+#define PTOTSR4_M_EXT0TMRSEL1 (1 << PTOTSR4_V_EXT0TMRSEL1)
#define PTOTSR4_V_EXT0TMRSELEN 3
-#define PTOTSR4_M_EXT0TMRSELEN 1 << PTOTSR4_V_EXT0TMRSELEN
+#define PTOTSR4_M_EXT0TMRSELEN (1 << PTOTSR4_V_EXT0TMRSELEN)
#define PTOTSR4_V_EXT1TMRSEL 4
-#define PTOTSR4_M_EXT1TMRSEL 0x3 << PTOTSR4_V_EXT1TMRSEL
+#define PTOTSR4_M_EXT1TMRSEL (0x3 << PTOTSR4_V_EXT1TMRSEL)
#define PTOTSR4_V_EXT1TMRSEL0 4
-#define PTOTSR4_M_EXT1TMRSEL0 1 << PTOTSR4_V_EXT1TMRSEL0
+#define PTOTSR4_M_EXT1TMRSEL0 (1 << PTOTSR4_V_EXT1TMRSEL0)
#define PTOTSR4_V_EXT1TMRSEL1 5
-#define PTOTSR4_M_EXT1TMRSEL1 1 << PTOTSR4_V_EXT1TMRSEL1
+#define PTOTSR4_M_EXT1TMRSEL1 (1 << PTOTSR4_V_EXT1TMRSEL1)
#define PTOTSR4_V_EXT1TMRSELEN 7
-#define PTOTSR4_M_EXT1TMRSELEN 1 << PTOTSR4_V_EXT1TMRSELEN
+#define PTOTSR4_M_EXT1TMRSELEN (1 << PTOTSR4_V_EXT1TMRSELEN)
#define PTOTSR4_V_EXT2TMRSEL 8
-#define PTOTSR4_M_EXT2TMRSEL 0x3 << PTOTSR4_V_EXT2TMRSEL
+#define PTOTSR4_M_EXT2TMRSEL (0x3 << PTOTSR4_V_EXT2TMRSEL)
#define PTOTSR4_V_EXT2TMRSEL0 8
-#define PTOTSR4_M_EXT2TMRSEL0 1 << PTOTSR4_V_EXT2TMRSEL0
+#define PTOTSR4_M_EXT2TMRSEL0 (1 << PTOTSR4_V_EXT2TMRSEL0)
#define PTOTSR4_V_EXT2TMRSEL1 9
-#define PTOTSR4_M_EXT2TMRSEL1 1 << PTOTSR4_V_EXT2TMRSEL1
+#define PTOTSR4_M_EXT2TMRSEL1 (1 << PTOTSR4_V_EXT2TMRSEL1)
#define PTOTSR4_V_EXT2TMRSELEN 11
-#define PTOTSR4_M_EXT2TMRSELEN 1 << PTOTSR4_V_EXT2TMRSELEN
+#define PTOTSR4_M_EXT2TMRSELEN (1 << PTOTSR4_V_EXT2TMRSELEN)
#define PTOTSR4_V_EXT3TMRSEL 12
-#define PTOTSR4_M_EXT3TMRSEL 0x3 << PTOTSR4_V_EXT3TMRSEL
+#define PTOTSR4_M_EXT3TMRSEL (0x3 << PTOTSR4_V_EXT3TMRSEL)
#define PTOTSR4_V_EXT3TMRSEL0 12
-#define PTOTSR4_M_EXT3TMRSEL0 1 << PTOTSR4_V_EXT3TMRSEL0
+#define PTOTSR4_M_EXT3TMRSEL0 (1 << PTOTSR4_V_EXT3TMRSEL0)
#define PTOTSR4_V_EXT3TMRSEL1 13
-#define PTOTSR4_M_EXT3TMRSEL1 1 << PTOTSR4_V_EXT3TMRSEL1
+#define PTOTSR4_M_EXT3TMRSEL1 (1 << PTOTSR4_V_EXT3TMRSEL1)
#define PTOTSR4_V_EXT3TMRSELEN 15
-#define PTOTSR4_M_EXT3TMRSELEN 1 << PTOTSR4_V_EXT3TMRSELEN
+#define PTOTSR4_M_EXT3TMRSELEN (1 << PTOTSR4_V_EXT3TMRSELEN)
/*
** EXTACT0 Activity Progammable Time-out Timer
@@ -2657,25 +2657,25 @@
*/
#define SR_POR_REG 0x100
#define POR_V_SEQUOIASEL 0
-#define POR_M_SEQUOIASEL 1 << POR_V_SEQUOIASEL
+#define POR_M_SEQUOIASEL (1 << POR_V_SEQUOIASEL)
#define POR_V_DLYBDEN 3
-#define POR_M_DLYBDEN 1 << POR_V_DLYBDEN
+#define POR_M_DLYBDEN (1 << POR_V_DLYBDEN)
#define POR_V_CPUMODESEL 4
-#define POR_M_CPUMODESEL 1 << POR_V_CPUMODESEL
+#define POR_M_CPUMODESEL (1 << POR_V_CPUMODESEL)
#define POR_V_DLYBDBUSEN 6
-#define POR_M_DLYBDBUSEN 1 << POR_V_DLYBDBUSEN
+#define POR_M_DLYBDBUSEN (1 << POR_V_DLYBDBUSEN)
#define POR_V_MISCCF 7
-#define POR_M_MISCCF 0x7 << POR_V_MISCCF
+#define POR_M_MISCCF (0x7 << POR_V_MISCCF)
#define POR_V_MISCCF0 7
-#define POR_M_MISCCF0 1 << POR_V_MISCCF0
+#define POR_M_MISCCF0 (1 << POR_V_MISCCF0)
#define POR_V_MISCCF1 8
-#define POR_M_MISCCF1 1 << POR_V_MISCCF1
+#define POR_M_MISCCF1 (1 << POR_V_MISCCF1)
#define POR_V_MISCCF2 9
-#define POR_M_MISCCF2 1 << POR_V_MISCCF2
+#define POR_M_MISCCF2 (1 << POR_V_MISCCF2)
#define POR_V_EXTRTC 11
-#define POR_M_EXTRTC 1 << POR_V_EXTRTC
+#define POR_M_EXTRTC (1 << POR_V_EXTRTC)
#define POR_V_1X2XCLKSEL 12
-#define POR_M_1X2XCLKSEL 1 << POR_V_1X2XCLKSEL
+#define POR_M_1X2XCLKSEL (1 << POR_V_1X2XCLKSEL)
/*
**
@@ -2692,15 +2692,15 @@
#define SR_NCR1R_REG 0x101
#define SR_NCR1R_INIT 0x0000
#define NCR1R_V_NCR1EN 0
-#define NCR1R_M_NCR1EN 1 << NCR1R_V_NCR1EN
+#define NCR1R_M_NCR1EN (1 << NCR1R_V_NCR1EN)
#define NCR1R_V_NCR1BS 1
-#define NCR1R_M_NCR1BS 0x3 << NCR1R_V_NCR1BS
+#define NCR1R_M_NCR1BS (0x3 << NCR1R_V_NCR1BS)
#define NCR1R_V_NCR1BS0 1
-#define NCR1R_M_NCR1BS0 1 << NCR1R_V_NCR1BS0
+#define NCR1R_M_NCR1BS0 (1 << NCR1R_V_NCR1BS0)
#define NCR1R_V_NCR1BS1 1
-#define NCR1R_M_NCR1BS1 1 << NCR1R_V_NCR1BS1
+#define NCR1R_M_NCR1BS1 (1 << NCR1R_V_NCR1BS1)
#define NCR1R_V_NCR1A 3
-#define NCR1R_M_NCR1A 0xFFF8 << NCR1R_V_NCR1A
+#define NCR1R_M_NCR1A (0xFFF8 << NCR1R_V_NCR1A)
/*
** Non-Cacheable Region 1 Block Size (Kbytes)
@@ -2725,15 +2725,15 @@
#define SR_NCR2R_REG 0x102
#define SR_NCR2R_INIT 0x0000
#define NCR2R_V_NCR2EN 0
-#define NCR2R_M_NCR2EN 1 << NCR2R_V_NCR2EN
+#define NCR2R_M_NCR2EN (1 << NCR2R_V_NCR2EN)
#define NCR2R_V_NCR2BS 1
-#define NCR2R_M_NCR2BS 0x3 << NCR2R_V_NCR2BS
+#define NCR2R_M_NCR2BS (0x3 << NCR2R_V_NCR2BS)
#define NCR2R_V_NCR2BS0 1
-#define NCR2R_M_NCR2BS0 1 << NCR2R_V_NCR2BS0
+#define NCR2R_M_NCR2BS0 (1 << NCR2R_V_NCR2BS0)
#define NCR2R_V_NCR2BS1 1
-#define NCR2R_M_NCR2BS1 1 << NCR2R_V_NCR2BS1
+#define NCR2R_M_NCR2BS1 (1 << NCR2R_V_NCR2BS1)
#define NCR2R_V_NCR2A 3
-#define NCR2R_M_NCR2A 0xFFF8 << NCR2R_V_NCR2A
+#define NCR2R_M_NCR2A (0xFFF8 << NCR2R_V_NCR2A)
/*
** Non-Cacheable Region 2 Block Size (Kbytes)
@@ -2770,35 +2770,35 @@
#define SR_SYSMCR1_REG 0x103
#define SR_SYSMCR1_INIT SYSMCR1_M_SMISEL
#define SYSMCR1_V_LDSMIHLDER 0
-#define SYSMCR1_M_LDSMIHLDER 1 << SYSMCR1_V_LDSMIHLDER
+#define SYSMCR1_M_LDSMIHLDER (1 << SYSMCR1_V_LDSMIHLDER)
#define SYSMCR1_V_MOVRLYEN 1
-#define SYSMCR1_M_MOVRLYEN 1 << SYSMCR1_V_MOVRLYEN
+#define SYSMCR1_M_MOVRLYEN (1 << SYSMCR1_V_MOVRLYEN)
#define SYSMCR1_V_SMMMAPSEL 2
-#define SYSMCR1_M_SMMMAPSEL 1 << SYSMCR1_V_SMMMAPSEL
+#define SYSMCR1_M_SMMMAPSEL (1 << SYSMCR1_V_SMMMAPSEL)
#define SYSMCR1_V_SMMDETECT 3
-#define SYSMCR1_M_SMMDETECT 1 << SYSMCR1_V_SMMDETECT
+#define SYSMCR1_M_SMMDETECT (1 << SYSMCR1_V_SMMDETECT)
#define SYSMCR1_V_FLUSHWSMI 4
-#define SYSMCR1_M_FLUSHWSMI 1 << SYSMCR1_V_FLUSHWSMI
+#define SYSMCR1_M_FLUSHWSMI (1 << SYSMCR1_V_FLUSHWSMI)
#define SYSMCR1_V_SMIFLUSHIN 5
-#define SYSMCR1_M_SMIFLUSHIN 1 << SYSMCR1_V_SMIFLUSHIN
+#define SYSMCR1_M_SMIFLUSHIN (1 << SYSMCR1_V_SMIFLUSHIN)
#define SYSMCR1_V_SMIFLUSHOUT 6
-#define SYSMCR1_M_SMIFLUSHOUT 1 << SYSMCR1_V_SMIFLUSHOUT
+#define SYSMCR1_M_SMIFLUSHOUT (1 << SYSMCR1_V_SMIFLUSHOUT)
#define SYSMCR1_V_SMMKENDIS 7
-#define SYSMCR1_M_SMMKENDIS 1 << SYSMCR1_V_SMMKENDIS
+#define SYSMCR1_M_SMMKENDIS (1 << SYSMCR1_V_SMMKENDIS)
#define SYSMCR1_V_KDISSMMREG 8
-#define SYSMCR1_M_KDISSMMREG 1 << SYSMCR1_V_KDISSMMREG
+#define SYSMCR1_M_KDISSMMREG (1 << SYSMCR1_V_KDISSMMREG)
#define SYSMCR1_V_SMISEL 9
-#define SYSMCR1_M_SMISEL 1 << SYSMCR1_V_SMISEL
+#define SYSMCR1_M_SMISEL (1 << SYSMCR1_V_SMISEL)
#define SYSMCR1_V_SMMBLASTL 10
-#define SYSMCR1_M_SMMBLASTL 1 << SYSMCR1_V_SMMBLASTL
+#define SYSMCR1_M_SMMBLASTL (1 << SYSMCR1_V_SMMBLASTL)
#define SYSMCR1_V_SMMMSKA20 11
-#define SYSMCR1_M_SMMMSKA20 1 << SYSMCR1_V_SMMMSKA20
+#define SYSMCR1_M_SMMMSKA20 (1 << SYSMCR1_V_SMMMSKA20)
#define SYSMCR1_V_SMMMAPD 13
-#define SYSMCR1_M_SMMMAPD 1 << SYSMCR1_V_SMMMAPD
+#define SYSMCR1_M_SMMMAPD (1 << SYSMCR1_V_SMMMAPD)
#define SYSMCR1_V_SMMMAPE 14
-#define SYSMCR1_M_SMMMAPE 1 << SYSMCR1_V_SMMMAPE
+#define SYSMCR1_M_SMMMAPE (1 << SYSMCR1_V_SMMMAPE)
#define SYSMCR1_V_SMISTRTSEL 15
-#define SYSMCR1_M_SMISTRTSEL 1 << SYSMCR1_V_SMISTRTSEL
+#define SYSMCR1_M_SMISTRTSEL (1 << SYSMCR1_V_SMISTRTSEL)
/*
**
@@ -2821,21 +2821,21 @@
#define SR_SYSMCR2_INIT ( SYSMCR2_M_SMIHLDOFRST | SYSMCR2_M_VLMSTLDOFF \
SYSMCR2_M_ENRDYN )
#define SYSMCR2_V_SMIHLDOFRST 0
-#define SYSMCR2_M_SMIHLDOFRST 1 << SYSMCR2_V_SMIHLDOFRST
+#define SYSMCR2_M_SMIHLDOFRST (1 << SYSMCR2_V_SMIHLDOFRST)
#define SYSMCR2_V_LCLKDIS 1
-#define SYSMCR2_M_LCLKDIS 1 << SYSMCR2_V_LCLKDIS
+#define SYSMCR2_M_LCLKDIS (1 << SYSMCR2_V_LCLKDIS)
#define SYSMCR2_V_KFLUSH 2
-#define SYSMCR2_M_KFLUSH 1 << SYSMCR2_V_KFLUSH
+#define SYSMCR2_M_KFLUSH (1 << SYSMCR2_V_KFLUSH)
#define SYSMCR2_V_LSTIOLTCHEN 4
-#define SYSMCR2_M_LSTIOLTCHEN 1 << SYSMCR2_V_LSTIOLTCHEN
+#define SYSMCR2_M_LSTIOLTCHEN (1 << SYSMCR2_V_LSTIOLTCHEN)
#define SYSMCR2_V_VLMSTLDOFF 6
-#define SYSMCR2_M_VLMSTLDOFF 1 << SYSMCR2_V_VLMSTLDOFF
+#define SYSMCR2_M_VLMSTLDOFF (1 << SYSMCR2_V_VLMSTLDOFF)
#define SYSMCR2_V_ENRDYN 13
-#define SYSMCR2_M_ENRDYN 1 << SYSMCR2_V_ENRDYN
+#define SYSMCR2_M_ENRDYN (1 << SYSMCR2_V_ENRDYN)
#define SYSMCR2_V_LMABLOCK 14
-#define SYSMCR2_M_LMABLOCK 1 << SYSMCR2_V_LMABLOCK
+#define SYSMCR2_M_LMABLOCK (1 << SYSMCR2_V_LMABLOCK)
#define SYSMCR2_V_SHDWRLOCK 15
-#define SYSMCR2_M_SHDWRLOCK 1 << SYSMCR2_V_SHDWRLOCK
+#define SYSMCR2_M_SHDWRLOCK (1 << SYSMCR2_V_SHDWRLOCK)
/*
**
@@ -2849,7 +2849,7 @@
*/
#define SR_PARADR1_REG 0x105
#define PARADR1_V_PARADR 2
-#define PARADR1_M_PARADR 0xFFFC << PARADR1_V_PARADR
+#define PARADR1_M_PARADR (0xFFFC << PARADR1_V_PARADR)
/*
**
@@ -2866,17 +2866,17 @@
*/
#define SR_PARADR2_REG 0x106
#define PARADR2_V_PARADR 0
-#define PARADR2_M_PARADR 0xFFF << PARADR2_V_PARADR
+#define PARADR2_M_PARADR (0xFFF << PARADR2_V_PARADR)
#define PARADR2_V_PARBE 12
-#define PARADR2_M_PARBE 0xF << PARADR2_V_PARBE
+#define PARADR2_M_PARBE (0xF << PARADR2_V_PARBE)
#define PARADR2_V_PARBE0 12
-#define PARADR2_M_PARBE0 1 << PARADR2_V_PARBE0
+#define PARADR2_M_PARBE0 (1 << PARADR2_V_PARBE0)
#define PARADR2_V_PARBE1 13
-#define PARADR2_M_PARBE1 1 << PARADR2_V_PARBE1
+#define PARADR2_M_PARBE1 (1 << PARADR2_V_PARBE1)
#define PARADR2_V_PARBE2 14
-#define PARADR2_M_PARBE2 1 << PARADR2_V_PARBE2
+#define PARADR2_M_PARBE2 (1 << PARADR2_V_PARBE2)
#define PARADR2_V_PARBE3 15
-#define PARADR2_M_PARBE3 1 << PARADR2_V_PARBE3
+#define PARADR2_M_PARBE3 (1 << PARADR2_V_PARBE3)
/*
** SEQUOIA-1 Pin Function Select Registers
@@ -2905,23 +2905,23 @@
#define SEQR_SEQPSR1_INIT ( SEQPSR1_M_PORT92DIS | SEQPSR1_M_CCSPINEN | \
SEQPSR1_M_TAGDEN)
#define SEQPSR1_V_NPWRGDDBDIS 0
-#define SEQPSR1_M_NPWRGDDBDIS 1 << SEQPSR1_V_NPWRGDDBDIS
+#define SEQPSR1_M_NPWRGDDBDIS (1 << SEQPSR1_V_NPWRGDDBDIS)
#define SEQPSR1_V_PORT92DIS 1
-#define SEQPSR1_M_PORT92DIS 1 << SEQPSR1_V_PORT92DIS
+#define SEQPSR1_M_PORT92DIS (1 << SEQPSR1_V_PORT92DIS)
#define SEQPSR1_V_TAGCSSEL 2
-#define SEQPSR1_M_TAGCSSEL 1 << SEQPSR1_V_TAGCSSEL
+#define SEQPSR1_M_TAGCSSEL (1 << SEQPSR1_V_TAGCSSEL)
#define SEQPSR1_V_LOCKPINSEL 3
-#define SEQPSR1_M_LOCKPINSEL 1 << SEQPSR1_V_LOCKPINSEL
+#define SEQPSR1_M_LOCKPINSEL (1 << SEQPSR1_V_LOCKPINSEL)
#define SEQPSR1_V_CCSPINEN 4
-#define SEQPSR1_M_CCSPINEN 1 << SEQPSR1_V_CCSPINEN
+#define SEQPSR1_M_CCSPINEN (1 << SEQPSR1_V_CCSPINEN)
#define SEQPSR1_V_TAGDEN 5
-#define SEQPSR1_M_TAGDEN 1 << SEQPSR1_V_TAGDEN
+#define SEQPSR1_M_TAGDEN (1 << SEQPSR1_V_TAGDEN)
#define SEQPSR1_V_GPIOC0PINEN 8
-#define SEQPSR1_M_GPIOC0PINEN 1 << SEQPSR1_V_GPIOC0PINEN
+#define SEQPSR1_M_GPIOC0PINEN (1 << SEQPSR1_V_GPIOC0PINEN)
#define SEQPSR1_V_HTRGOUTEN 10
-#define SEQPSR1_M_HTRGOUTEN 1 << SEQPSR1_V_HTRGOUTEN
+#define SEQPSR1_M_HTRGOUTEN (1 << SEQPSR1_V_HTRGOUTEN)
#define SEQPSR1_V_GPIOA0PINEN 11
-#define SEQPSR1_M_GPIOA0PINEN 1 << SEQPSR1_V_GPIOA0PINEN
+#define SEQPSR1_M_GPIOA0PINEN (1 << SEQPSR1_V_GPIOA0PINEN)
/*
**
@@ -2952,35 +2952,35 @@
SEQPSR2_M_BIT9 | SEQPSR2_M_BIT10 |\
SEQPSR2_M_GPIOC1PINEN )
#define SEQPSR2_V_OPGPEXTEN 0
-#define SEQPSR2_M_OPGPEXTEN 1 << SEQPSR2_V_OPGPEXTEN
+#define SEQPSR2_M_OPGPEXTEN (1 << SEQPSR2_V_OPGPEXTEN)
#define SEQPSR2_V_EXTACT3PINEN 2
-#define SEQPSR2_M_EXTACT3PINEN 1 << SEQPSR2_V_EXTACT3PINEN
+#define SEQPSR2_M_EXTACT3PINEN (1 << SEQPSR2_V_EXTACT3PINEN)
#define SEQPSR2_V_NMIPINEN 3
-#define SEQPSR2_M_NMIPINEN 1 << SEQPSR2_V_NMIPINEN
+#define SEQPSR2_M_NMIPINEN (1 << SEQPSR2_V_NMIPINEN)
#define SEQPSR2_V_DIRTYPINEN 4
-#define SEQPSR2_M_DIRTYPINEN 1 << SEQPSR2_V_DIRTYPINEN
+#define SEQPSR2_M_DIRTYPINEN (1 << SEQPSR2_V_DIRTYPINEN)
#define SEQPSR2_V_GPIOB0PINEN 5
-#define SEQPSR2_M_GPIOB0PINEN 1 << SEQPSR2_V_GPIOB0PINEN
+#define SEQPSR2_M_GPIOB0PINEN (1 << SEQPSR2_V_GPIOB0PINEN)
#define SEQPSR2_V_DRTWEPINEN 6
-#define SEQPSR2_M_DRTWEPINEN 1 << SEQPSR2_V_DRTWEPINEN
+#define SEQPSR2_M_DRTWEPINEN (1 << SEQPSR2_V_DRTWEPINEN)
#define SEQPSR2_V_GPIOB1PINEN 7
-#define SEQPSR2_M_GPIOB1PINEN 1 << SEQPSR2_V_GPIOB1PINEN
+#define SEQPSR2_M_GPIOB1PINEN (1 << SEQPSR2_V_GPIOB1PINEN)
#define SEQPSR2_V_KBRSTPINEN 8
-#define SEQPSR2_M_KBRSTPINEN 1 << SEQPSR2_V_KBRSTPINEN
+#define SEQPSR2_M_KBRSTPINEN (1 << SEQPSR2_V_KBRSTPINEN)
#define SEQPSR2_V_BIT9 9
-#define SEQPSR2_M_BIT9 1 << SEQPSR2_V_BIT9
+#define SEQPSR2_M_BIT9 (1 << SEQPSR2_V_BIT9)
#define SEQPSR2_V_BIT10 10
-#define SEQPSR2_M_BIT10 1 << SEQPSR2_V_BIT10
+#define SEQPSR2_M_BIT10 (1 << SEQPSR2_V_BIT10)
#define SEQPSR2_V_GPIOC1PINEN 11
-#define SEQPSR2_M_GPIOC1PINEN 1 << SEQPSR2_V_GPIOC1PINEN
+#define SEQPSR2_M_GPIOC1PINEN (1 << SEQPSR2_V_GPIOC1PINEN)
#define SEQPSR2_V_GPIO0PINEN 12
-#define SEQPSR2_M_GPIO0PINEN 1 << SEQPSR2_V_GPIO0PINEN
+#define SEQPSR2_M_GPIO0PINEN (1 << SEQPSR2_V_GPIO0PINEN)
#define SEQPSR2_V_GPIO1PINEN 13
-#define SEQPSR2_M_GPIO1PINEN 1 << SEQPSR2_V_GPIO1PINEN
+#define SEQPSR2_M_GPIO1PINEN (1 << SEQPSR2_V_GPIO1PINEN)
#define SEQPSR2_V_GPIO2PINEN 14
-#define SEQPSR2_M_GPIO2PINEN 1 << SEQPSR2_V_GPIO2PINEN
+#define SEQPSR2_M_GPIO2PINEN (1 << SEQPSR2_V_GPIO2PINEN)
#define SEQPSR2_V_GPIO3PINEN 15
-#define SEQPSR2_M_GPIO3PINEN 1 << SEQPSR2_V_GPIO3PINEN
+#define SEQPSR2_M_GPIO3PINEN (1 << SEQPSR2_V_GPIO3PINEN)
/*
**
@@ -3008,27 +3008,27 @@
SEQPSR3_M_PC6PINEN | SEQPSR3_M_PC7PINEN | \
SEQPSR3_M_PC8PINEN | SEQPSR3_M_PC9PINEN )
#define SEQPSR3_V_PC0PINEN 0
-#define SEQPSR3_M_PC0PINEN 1U << SEQPSR3_V_PC0PINEN
+#define SEQPSR3_M_PC0PINEN (1U << SEQPSR3_V_PC0PINEN)
#define SEQPSR3_V_PC2PINEN 2
-#define SEQPSR3_M_PC2PINEN 1U << SEQPSR3_V_PC2PINEN
+#define SEQPSR3_M_PC2PINEN (1U << SEQPSR3_V_PC2PINEN)
#define SEQPSR3_V_PC3PINEN 3
-#define SEQPSR3_M_PC3PINEN 1U << SEQPSR3_V_PC3PINEN
+#define SEQPSR3_M_PC3PINEN (1U << SEQPSR3_V_PC3PINEN)
#define SEQPSR3_V_PC4PINEN 4
-#define SEQPSR3_M_PC4PINEN 1U << SEQPSR3_V_PC4PINEN
+#define SEQPSR3_M_PC4PINEN (1U << SEQPSR3_V_PC4PINEN)
#define SEQPSR3_V_PC5PINEN 5
-#define SEQPSR3_M_PC5PINEN 1U << SEQPSR3_V_PC5PINEN
+#define SEQPSR3_M_PC5PINEN (1U << SEQPSR3_V_PC5PINEN)
#define SEQPSR3_V_PC6PINEN 6
-#define SEQPSR3_M_PC6PINEN 1U << SEQPSR3_V_PC6PINEN
+#define SEQPSR3_M_PC6PINEN (1U << SEQPSR3_V_PC6PINEN)
#define SEQPSR3_V_PC7PINEN 7
-#define SEQPSR3_M_PC7PINEN 1U << SEQPSR3_V_PC7PINEN
+#define SEQPSR3_M_PC7PINEN (1U << SEQPSR3_V_PC7PINEN)
#define SEQPSR3_V_PC8PINEN 8
-#define SEQPSR3_M_PC8PINEN 1U << SEQPSR3_V_PC8PINEN
+#define SEQPSR3_M_PC8PINEN (1U << SEQPSR3_V_PC8PINEN)
#define SEQPSR3_V_PC9PINEN 9
-#define SEQPSR3_M_PC9PINEN 1U << SEQPSR3_V_PC9PINEN
+#define SEQPSR3_M_PC9PINEN (1U << SEQPSR3_V_PC9PINEN)
#define SEQPSR3_V_EXTACT0PINEN 12
-#define SEQPSR3_M_EXTACT0PINEN 1U << SEQPSR3_V_EXTACT0PINEN
+#define SEQPSR3_M_EXTACT0PINEN (1U << SEQPSR3_V_EXTACT0PINEN)
#define SEQPSR3_V_EXTACT1PINEN 15
-#define SEQPSR3_M_EXTACT1PINEN 1U << SEQPSR3_V_EXTACT1PINEN
+#define SEQPSR3_M_EXTACT1PINEN (1U << SEQPSR3_V_EXTACT1PINEN)
/*
**
@@ -3046,13 +3046,13 @@
#define SEQR_MODCLKCR_REG 0x118
#define SEQR_MODCLKCR_INIT MODCLKCR_M_VLCLKSTPEN
#define MODCLKCR_V_VLCLKSTPEN 1
-#define MODCLKCR_M_VLCLKSTPEN 1 << MODCLKCR_V_VLCLKSTPEN
+#define MODCLKCR_M_VLCLKSTPEN (1 << MODCLKCR_V_VLCLKSTPEN)
#define MODCLKCR_V_ADSMDIS 5
-#define MODCLKCR_M_ADSMDIS 1 << MODCLKCR_V_ADSMDIS
+#define MODCLKCR_M_ADSMDIS (1 << MODCLKCR_V_ADSMDIS)
#define MODCLKCR_V_MDCHGIMD 8
-#define MODCLKCR_M_MDCHGIMD 1 << MODCLKCR_V_MDCHGIMD
+#define MODCLKCR_M_MDCHGIMD (1 << MODCLKCR_V_MDCHGIMD)
#define MODCLKCR_V_SLWATCKEN 11
-#define MODCLKCR_M_SLWWATCKEN 1 << MODCLKCR_V_SLWATCKEN
+#define MODCLKCR_M_SLWWATCKEN (1 << MODCLKCR_V_SLWATCKEN)
/*
**
@@ -3068,11 +3068,11 @@
*/
#define SEQR_BBUSCR_REG 0x180
#define BBUSCR_V_SQ1GIDEEN 3
-#define BBUSCR_M_SQ1GIDEEN 1 << BBUSCR_V_SQ1GIDEEN
+#define BBUSCR_M_SQ1GIDEEN (1 << BBUSCR_V_SQ1GIDEEN)
#define BBUSCR_V_RSTREADSEN 5
-#define BBUSCR_M_RSTREADSEN 1 << BBUSCR_V_RSTREADSEN
+#define BBUSCR_M_RSTREADSEN (1 << BBUSCR_V_RSTREADSEN)
#define BBUSCR_V_SECIDEN 15
-#define BBUSCR_M_SECIDEN 1 << BBUSCR_V_SECIDEN
+#define BBUSCR_M_SECIDEN (1 << BBUSCR_V_SECIDEN)
/*
** DRAM Control Registers
@@ -3104,31 +3104,31 @@
#define DRAMCR_SRAMRDENCR_REG 0x200
#define DRAMCR_SRAMRDENCR_INIT 0x0000
#define SRAMRDENCR_V_LMEMRDEN0 0
-#define SRAMRDENCR_M_LMEMRDEN0 1 << SRAMRDENCR_V_LMEMRDEN0
+#define SRAMRDENCR_M_LMEMRDEN0 (1 << SRAMRDENCR_V_LMEMRDEN0)
#define SRAMRDENCR_V_LMEMRDEN1 1
-#define SRAMRDENCR_M_LMEMRDEN1 1 << SRAMRDENCR_V_LMEMRDEN1
+#define SRAMRDENCR_M_LMEMRDEN1 (1 << SRAMRDENCR_V_LMEMRDEN1)
#define SRAMRDENCR_V_LMEMRDEN2 2
-#define SRAMRDENCR_M_LMEMRDEN2 1 << SRAMRDENCR_V_LMEMRDEN2
+#define SRAMRDENCR_M_LMEMRDEN2 (1 << SRAMRDENCR_V_LMEMRDEN2)
#define SRAMRDENCR_V_LMEMRDEN3 3
-#define SRAMRDENCR_M_LMEMRDEN3 1 << SRAMRDENCR_V_LMEMRDEN3
+#define SRAMRDENCR_M_LMEMRDEN3 (1 << SRAMRDENCR_V_LMEMRDEN3)
#define SRAMRDENCR_V_LMEMRDEN4 4
-#define SRAMRDENCR_M_LMEMRDEN4 1 << SRAMRDENCR_V_LMEMRDEN4
+#define SRAMRDENCR_M_LMEMRDEN4 (1 << SRAMRDENCR_V_LMEMRDEN4)
#define SRAMRDENCR_V_LMEMRDEN5 5
-#define SRAMRDENCR_M_LMEMRDEN5 1 << SRAMRDENCR_V_LMEMRDEN5
+#define SRAMRDENCR_M_LMEMRDEN5 (1 << SRAMRDENCR_V_LMEMRDEN5)
#define SRAMRDENCR_V_LMEMRDEN6 6
-#define SRAMRDENCR_M_LMEMRDEN6 1 << SRAMRDENCR_V_LMEMRDEN6
+#define SRAMRDENCR_M_LMEMRDEN6 (1 << SRAMRDENCR_V_LMEMRDEN6)
#define SRAMRDENCR_V_LMEMRDEN7 7
-#define SRAMRDENCR_M_LMEMRDEN7 1 << SRAMRDENCR_V_LMEMRDEN7
+#define SRAMRDENCR_M_LMEMRDEN7 (1 << SRAMRDENCR_V_LMEMRDEN7)
#define SRAMRDENCR_V_LMEMRDEN8 8
-#define SRAMRDENCR_M_LMEMRDEN8 1 << SRAMRDENCR_V_LMEMRDEN8
+#define SRAMRDENCR_M_LMEMRDEN8 (1 << SRAMRDENCR_V_LMEMRDEN8)
#define SRAMRDENCR_V_LMEMRDEN9 9
-#define SRAMRDENCR_M_LMEMRDEN9 1 << SRAMRDENCR_V_LMEMRDEN9
+#define SRAMRDENCR_M_LMEMRDEN9 (1 << SRAMRDENCR_V_LMEMRDEN9)
#define SRAMRDENCR_V_LMEMRDEN10 10
-#define SRAMRDENCR_M_LMEMRDEN10 1 << SRAMRDENCR_V_LMEMRDEN10
+#define SRAMRDENCR_M_LMEMRDEN10 (1 << SRAMRDENCR_V_LMEMRDEN10)
#define SRAMRDENCR_V_LMEMRDEN11 11
-#define SRAMRDENCR_M_LMEMRDEN11 1 << SRAMRDENCR_V_LMEMRDEN11
+#define SRAMRDENCR_M_LMEMRDEN11 (1 << SRAMRDENCR_V_LMEMRDEN11)
#define SRAMRDENCR_V_LMEMRDEN12 12
-#define SRAMRDENCR_M_LMEMRDEN12 1 << SRAMRDENCR_V_LMEMRDEN12
+#define SRAMRDENCR_M_LMEMRDEN12 (1 << SRAMRDENCR_V_LMEMRDEN12)
/*
**
@@ -3155,31 +3155,31 @@
#define DRAMCR_SRAMWRENCR_REG 0x201
#define DRAMCR_SRAMWRENCR_INIT 0x0000
#define SRAMWRENCR_V_LMEMWREN0 0
-#define SRAMWRENCR_M_LMEMWREN0 1 << SRAMWRENCR_V_LMEMWREN0
+#define SRAMWRENCR_M_LMEMWREN0 (1 << SRAMWRENCR_V_LMEMWREN0)
#define SRAMWRENCR_V_LMEMWREN1 1
-#define SRAMWRENCR_M_LMEMWREN1 1 << SRAMWRENCR_V_LMEMWREN1
+#define SRAMWRENCR_M_LMEMWREN1 (1 << SRAMWRENCR_V_LMEMWREN1)
#define SRAMWRENCR_V_LMEMWREN2 2
-#define SRAMWRENCR_M_LMEMWREN2 1 << SRAMWRENCR_V_LMEMWREN2
+#define SRAMWRENCR_M_LMEMWREN2 (1 << SRAMWRENCR_V_LMEMWREN2)
#define SRAMWRENCR_V_LMEMWREN3 3
-#define SRAMWRENCR_M_LMEMWREN3 1 << SRAMWRENCR_V_LMEMWREN3
+#define SRAMWRENCR_M_LMEMWREN3 (1 << SRAMWRENCR_V_LMEMWREN3)
#define SRAMWRENCR_V_LMEMWREN4 4
-#define SRAMWRENCR_M_LMEMWREN4 1 << SRAMWRENCR_V_LMEMWREN4
+#define SRAMWRENCR_M_LMEMWREN4 (1 << SRAMWRENCR_V_LMEMWREN4)
#define SRAMWRENCR_V_LMEMWREN5 5
-#define SRAMWRENCR_M_LMEMWREN5 1 << SRAMWRENCR_V_LMEMWREN5
+#define SRAMWRENCR_M_LMEMWREN5 (1 << SRAMWRENCR_V_LMEMWREN5)
#define SRAMWRENCR_V_LMEMWREN6 6
-#define SRAMWRENCR_M_LMEMWREN6 1 << SRAMWRENCR_V_LMEMWREN6
+#define SRAMWRENCR_M_LMEMWREN6 (1 << SRAMWRENCR_V_LMEMWREN6)
#define SRAMWRENCR_V_LMEMWREN7 7
-#define SRAMWRENCR_M_LMEMWREN7 1 << SRAMWRENCR_V_LMEMWREN7
+#define SRAMWRENCR_M_LMEMWREN7 (1 << SRAMWRENCR_V_LMEMWREN7)
#define SRAMWRENCR_V_LMEMWREN8 8
-#define SRAMWRENCR_M_LMEMWREN8 1 << SRAMWRENCR_V_LMEMWREN8
+#define SRAMWRENCR_M_LMEMWREN8 (1 << SRAMWRENCR_V_LMEMWREN8)
#define SRAMWRENCR_V_LMEMWREN9 9
-#define SRAMWRENCR_M_LMEMWREN9 1 << SRAMWRENCR_V_LMEMWREN9
+#define SRAMWRENCR_M_LMEMWREN9 (1 << SRAMWRENCR_V_LMEMWREN9)
#define SRAMWRENCR_V_LMEMWREN10 10
-#define SRAMWRENCR_M_LMEMWREN10 1 << SRAMWRENCR_V_LMEMWREN10
+#define SRAMWRENCR_M_LMEMWREN10 (1 << SRAMWRENCR_V_LMEMWREN10)
#define SRAMWRENCR_V_LMEMWREN11 11
-#define SRAMWRENCR_M_LMEMWREN11 1 << SRAMWRENCR_V_LMEMWREN11
+#define SRAMWRENCR_M_LMEMWREN11 (1 << SRAMWRENCR_V_LMEMWREN11)
#define SRAMWRENCR_V_LMEMWREN12 12
-#define SRAMWRENCR_M_LMEMWREN12 1 << SRAMWRENCR_V_LMEMWREN12
+#define SRAMWRENCR_M_LMEMWREN12 (1 << SRAMWRENCR_V_LMEMWREN12)
/*
**
@@ -3201,27 +3201,27 @@
#define DRAMCR_BK0CR_REG 0x202
#define DRAMCR_BK0CR_INIT 0x0000
#define BK0CR_V_B0A 0
-#define BK0CR_M_B0A 0xFF << BK0CR_V_B0A
+#define BK0CR_M_B0A (0xFF << BK0CR_V_B0A)
#define BK0CR_V_B0S 8
-#define BK0CR_M_B0S 0x7 << BK0CR_V_B0S
+#define BK0CR_M_B0S (0x7 << BK0CR_V_B0S)
#define BK0CR_V_B0S0 8
-#define BK0CR_M_B0S0 1 << BK0CR_V_B0S0
+#define BK0CR_M_B0S0 (1 << BK0CR_V_B0S0)
#define BK0CR_V_B0S1 9
-#define BK0CR_M_B0S1 1 << BK0CR_V_B0S1
+#define BK0CR_M_B0S1 (1 << BK0CR_V_B0S1)
#define BK0CR_V_B0S2 10
-#define BK0CR_M_B0S2 1 << BK0CR_V_B0S2
+#define BK0CR_M_B0S2 (1 << BK0CR_V_B0S2)
#define BK0CR_V_BANKEN0 11
-#define BK0CR_M_BANKEN0 1 << BK0CR_V_BANKEN0
+#define BK0CR_M_BANKEN0 (1 << BK0CR_V_BANKEN0)
#define BK0CR_V_ENMDEN0N 12
-#define BK0CR_M_ENMDEN0N 1 << BK0CR_V_ENMDEN0N
+#define BK0CR_M_ENMDEN0N (1 << BK0CR_V_ENMDEN0N)
#define BK0CR_V_COLADR0 13
-#define BK0CR_M_COLADR0 0xE << BK0CR_V_COLADR0
+#define BK0CR_M_COLADR0 (0xE << BK0CR_V_COLADR0)
#define BK0CR_V_COLADR00 13
-#define BK0CR_M_COLADR00 1 << BK0CR_V_COLADR00
+#define BK0CR_M_COLADR00 (1 << BK0CR_V_COLADR00)
#define BK0CR_V_COLADR01 14
-#define BK0CR_M_COLADR01 1 << BK0CR_V_COLADR01
+#define BK0CR_M_COLADR01 (1 << BK0CR_V_COLADR01)
#define BK0CR_V_COLADR02 15
-#define BK0CR_M_COLADR02 1 << BK0CR_V_COLADR02
+#define BK0CR_M_COLADR02 (1 << BK0CR_V_COLADR02)
/*
** Bank 0 DRAM Size
@@ -3262,27 +3262,27 @@
#define DRAMCR_BK1CR_REG 0x203
#define DRAMCR_BK1CR_INIT 0x0000
#define BK1CR_V_B1A 0
-#define BK1CR_M_B1A 0xFF << BK1CR_V_B1A
+#define BK1CR_M_B1A (0xFF << BK1CR_V_B1A)
#define BK1CR_V_B1S 8
-#define BK1CR_M_B1S 0x7 << BK1CR_V_B1S
+#define BK1CR_M_B1S (0x7 << BK1CR_V_B1S)
#define BK1CR_V_B1S0 8
-#define BK1CR_M_B1S0 1 << BK1CR_V_B1S0
+#define BK1CR_M_B1S0 (1 << BK1CR_V_B1S0)
#define BK1CR_V_B1S1 9
-#define BK1CR_M_B1S1 1 << BK1CR_V_B1S1
+#define BK1CR_M_B1S1 (1 << BK1CR_V_B1S1)
#define BK1CR_V_B1S2 10
-#define BK1CR_M_B1S2 1 << BK1CR_V_B1S2
+#define BK1CR_M_B1S2 (1 << BK1CR_V_B1S2)
#define BK1CR_V_BANKEN1 11
-#define BK1CR_M_BANKEN1 1 << BK1CR_V_BANKEN1
+#define BK1CR_M_BANKEN1 (1 << BK1CR_V_BANKEN1)
#define BK1CR_V_ENMDEN1N 12
-#define BK1CR_M_ENMDEN1N 1 << BK1CR_V_ENMDEN1N
+#define BK1CR_M_ENMDEN1N (1 << BK1CR_V_ENMDEN1N)
#define BK1CR_V_COLADR1 13
-#define BK1CR_M_COLADR1 0xE << BK1CR_V_COLADR1
+#define BK1CR_M_COLADR1 (0xE << BK1CR_V_COLADR1)
#define BK1CR_V_COLADR10 13
-#define BK1CR_M_COLADR10 1 << BK1CR_V_COLADR10
+#define BK1CR_M_COLADR10 (1 << BK1CR_V_COLADR10)
#define BK1CR_V_COLADR11 14
-#define BK1CR_M_COLADR11 1 << BK1CR_V_COLADR11
+#define BK1CR_M_COLADR11 (1 << BK1CR_V_COLADR11)
#define BK1CR_V_COLADR12 15
-#define BK1CR_M_COLADR12 1 << BK1CR_V_COLADR12
+#define BK1CR_M_COLADR12 (1 << BK1CR_V_COLADR12)
/*
** Bank 1 DRAM Size
@@ -3333,39 +3333,39 @@
BK01TCR_M_B01MATC | BK01TCR_M_B01RPRE | \
BK01TCR_M_B01ILAVDT )
#define BK01TCR_V_B01WRCPW 0
-#define BK01TCR_M_B01WRCPW 0x3 << BK01TCR_V_B01WRCPW
+#define BK01TCR_M_B01WRCPW (0x3 << BK01TCR_V_B01WRCPW)
#define BK01TCR_V_B01WRCPW0 0
-#define BK01TCR_M_B01WRCPW0 1 << BK01TCR_V_B01WRCPW0
+#define BK01TCR_M_B01WRCPW0 (1 << BK01TCR_V_B01WRCPW0)
#define BK01TCR_V_B01WRCPW1 1
-#define BK01TCR_M_B01WRCPW1 1 << BK01TCR_V_B01WRCPW1
+#define BK01TCR_M_B01WRCPW1 (1 << BK01TCR_V_B01WRCPW1)
#define BK01TCR_V_MA01WRDLY 2
-#define BK01TCR_M_MA01WRDLY 1 << BK01TCR_V_MA01WRDLY
+#define BK01TCR_M_MA01WRDLY (1 << BK01TCR_V_MA01WRDLY)
#define BK01TCR_V_B01RDCPW 3
-#define BK01TCR_M_B01RDCPW 0x3 << BK01TCR_V_B01RDCPW
+#define BK01TCR_M_B01RDCPW (0x3 << BK01TCR_V_B01RDCPW)
#define BK01TCR_V_B01RDCPW0 3
-#define BK01TCR_M_B01RDCPW0 1 << BK01TCR_V_B01RDCPW0
+#define BK01TCR_M_B01RDCPW0 (1 << BK01TCR_V_B01RDCPW0)
#define BK01TCR_V_B01RDCPW1 4
-#define BK01TCR_M_B01RDCPW1 1 << BK01TCR_V_B01RDCPW1
+#define BK01TCR_M_B01RDCPW1 (1 << BK01TCR_V_B01RDCPW1)
#define BK01TCR_V_MA01RDDLY 5
-#define BK01TCR_M_MA01RDDLY 1 << BK01TCR_V_MA01RDDLY
+#define BK01TCR_M_MA01RDDLY (1 << BK01TCR_V_MA01RDDLY)
#define BK01TCR_V_B01CPRE 6
-#define BK01TCR_M_B01CPRE 1 << BK01TCR_V_B01CPRE
+#define BK01TCR_M_B01CPRE (1 << BK01TCR_V_B01CPRE)
#define BK01TCR_V_B01RTMA 7
-#define BK01TCR_M_B01RTMA 1 << BK01TCR_V_B01RTMA
+#define BK01TCR_M_B01RTMA (1 << BK01TCR_V_B01RTMA)
#define BK01TCR_V_B01MATC 8
-#define BK01TCR_M_B01MATC 1 << BK01TCR_V_B01MATC
+#define BK01TCR_M_B01MATC (1 << BK01TCR_V_B01MATC)
#define BK01TCR_V_B01RPRE 9
-#define BK01TCR_M_B01RPRE 0x7 << BK01TCR_V_B01RPRE
+#define BK01TCR_M_B01RPRE (0x7 << BK01TCR_V_B01RPRE)
#define BK01TCR_V_B01RPRE0 9
-#define BK01TCR_M_B01RPRE0 1 << BK01TCR_V_B01RPRE0
+#define BK01TCR_M_B01RPRE0 (1 << BK01TCR_V_B01RPRE0)
#define BK01TCR_V_B01RPRE1 10
-#define BK01TCR_M_B01RPRE1 1 << BK01TCR_V_B01RPRE1
+#define BK01TCR_M_B01RPRE1 (1 << BK01TCR_V_B01RPRE1)
#define BK01TCR_V_B01RPRE2 11
-#define BK01TCR_M_B01RPRE2 1 << BK01TCR_V_B01RPRE2
+#define BK01TCR_M_B01RPRE2 (1 << BK01TCR_V_B01RPRE2)
#define BK01TCR_V_B01ILAVDT 12
-#define BK01TCR_M_B01ILAVDT 1 << BK01TCR_V_B01ILAVDT
+#define BK01TCR_M_B01ILAVDT (1 << BK01TCR_V_B01ILAVDT)
#define BK01TCR_V_BNK01_ITL 13
-#define BK01TCR_M_BNK01_ITL 1 << BK01TCR_V_BNK01_ITL
+#define BK01TCR_M_BNK01_ITL (1 << BK01TCR_V_BNK01_ITL)
/*
** Bank 0/1 Write CAS Cycle Time
@@ -3412,27 +3412,27 @@
#define DRAMCR_BK2CR_REG 0x205
#define DRAMCR_BK2CR_INIT 0x0000
#define BK2CR_V_B2A 0
-#define BK2CR_M_B2A 0xFF << BK2CR_V_B2A
+#define BK2CR_M_B2A (0xFF << BK2CR_V_B2A)
#define BK2CR_V_B2S 8
-#define BK2CR_M_B2S 0x7 << BK2CR_V_B2S
+#define BK2CR_M_B2S (0x7 << BK2CR_V_B2S)
#define BK2CR_V_B2S0 8
-#define BK2CR_M_B2S0 1 << BK2CR_V_B2S0
+#define BK2CR_M_B2S0 (1 << BK2CR_V_B2S0)
#define BK2CR_V_B2S1 9
-#define BK2CR_M_B2S1 1 << BK2CR_V_B2S1
+#define BK2CR_M_B2S1 (1 << BK2CR_V_B2S1)
#define BK2CR_V_B2S2 10
-#define BK2CR_M_B2S2 1 << BK2CR_V_B2S2
+#define BK2CR_M_B2S2 (1 << BK2CR_V_B2S2)
#define BK2CR_V_BANKEN2 11
-#define BK2CR_M_BANKEN2 1 << BK2CR_V_BANKEN2
+#define BK2CR_M_BANKEN2 (1 << BK2CR_V_BANKEN2)
#define BK2CR_V_ENMDEN2N 12
-#define BK2CR_M_ENMDEN2N 1 << BK2CR_V_ENMDEN2N
+#define BK2CR_M_ENMDEN2N (1 << BK2CR_V_ENMDEN2N)
#define BK2CR_V_COLADR2 13
-#define BK2CR_M_COLADR2 0xE << BK2CR_V_COLADR2
+#define BK2CR_M_COLADR2 (0xE << BK2CR_V_COLADR2)
#define BK2CR_V_COLADR20 13
-#define BK2CR_M_COLADR20 1 << BK2CR_V_COLADR20
+#define BK2CR_M_COLADR20 (1 << BK2CR_V_COLADR20)
#define BK2CR_V_COLADR21 14
-#define BK2CR_M_COLADR21 1 << BK2CR_V_COLADR21
+#define BK2CR_M_COLADR21 (1 << BK2CR_V_COLADR21)
#define BK2CR_V_COLADR22 15
-#define BK2CR_M_COLADR22 1 << BK2CR_V_COLADR22
+#define BK2CR_M_COLADR22 (1 << BK2CR_V_COLADR22)
/*
** Bank 2 DRAM Size
@@ -3473,27 +3473,27 @@
#define DRAMCR_BK3CR_REG 0x206
#define DRAMCR_BK3CR_INIT 0x0000
#define BK3CR_V_B3A 0
-#define BK3CR_M_B3A 0xFF << BK3CR_V_B3A
+#define BK3CR_M_B3A (0xFF << BK3CR_V_B3A)
#define BK3CR_V_B3S 8
-#define BK3CR_M_B3S 0x7 << BK3CR_V_B3S
+#define BK3CR_M_B3S (0x7 << BK3CR_V_B3S)
#define BK3CR_V_B3S0 8
-#define BK3CR_M_B3S0 1 << BK3CR_V_B3S0
+#define BK3CR_M_B3S0 (1 << BK3CR_V_B3S0)
#define BK3CR_V_B3S1 9
-#define BK3CR_M_B3S1 1 << BK3CR_V_B3S1
+#define BK3CR_M_B3S1 (1 << BK3CR_V_B3S1)
#define BK3CR_V_B3S2 10
-#define BK3CR_M_B3S2 1 << BK3CR_V_B3S2
+#define BK3CR_M_B3S2 (1 << BK3CR_V_B3S2)
#define BK3CR_V_BANKEN3 11
-#define BK3CR_M_BANKEN3 1 << BK3CR_V_BANKEN3
+#define BK3CR_M_BANKEN3 (1 << BK3CR_V_BANKEN3)
#define BK3CR_V_ENMDEN3N 12
-#define BK3CR_M_ENMDEN3N 1 << BK3CR_V_ENMDEN3N
+#define BK3CR_M_ENMDEN3N (1 << BK3CR_V_ENMDEN3N)
#define BK3CR_V_COLADR3 13
-#define BK3CR_M_COLADR3 0xE << BK3CR_V_COLADR3
+#define BK3CR_M_COLADR3 (0xE << BK3CR_V_COLADR3)
#define BK3CR_V_COLADR30 13
-#define BK3CR_M_COLADR30 1 << BK3CR_V_COLADR30
+#define BK3CR_M_COLADR30 (1 << BK3CR_V_COLADR30)
#define BK3CR_V_COLADR31 14
-#define BK3CR_M_COLADR31 1 << BK3CR_V_COLADR31
+#define BK3CR_M_COLADR31 (1 << BK3CR_V_COLADR31)
#define BK3CR_V_COLADR32 15
-#define BK3CR_M_COLADR32 1 << BK3CR_V_COLADR32
+#define BK3CR_M_COLADR32 (1 << BK3CR_V_COLADR32)
/*
** Bank 3 DRAM Size
@@ -3542,37 +3542,37 @@
BK23TCR_M_B23CPRE | BK23TCR_M_B23RTMA | \
BK23TCR_M_B23MATC | BK23TCR_M_B23RPRE )
#define BK23TCR_V_B23WRCPW 0
-#define BK23TCR_M_B23WRCPW 0x3 << BK23TCR_V_B23WRCPW
+#define BK23TCR_M_B23WRCPW (0x3 << BK23TCR_V_B23WRCPW)
#define BK23TCR_V_B23WRCPW0 0
-#define BK23TCR_M_B23WRCPW0 1 << BK23TCR_V_B23WRCPW0
+#define BK23TCR_M_B23WRCPW0 (1 << BK23TCR_V_B23WRCPW0)
#define BK23TCR_V_B23WRCPW1 1
-#define BK23TCR_M_B23WRCPW1 1 << BK23TCR_V_B23WRCPW1
+#define BK23TCR_M_B23WRCPW1 (1 << BK23TCR_V_B23WRCPW1)
#define BK23TCR_V_MA23WRDLY 2
-#define BK23TCR_M_MA23WRDLY 1 << BK23TCR_V_MA23WRDLY
+#define BK23TCR_M_MA23WRDLY (1 << BK23TCR_V_MA23WRDLY)
#define BK23TCR_V_B23RDCPW 3
-#define BK23TCR_M_B23RDCPW 0x3 << BK23TCR_V_B23RDCPW
+#define BK23TCR_M_B23RDCPW (0x3 << BK23TCR_V_B23RDCPW)
#define BK23TCR_V_B23RDCPW0 3
-#define BK23TCR_M_B23RDCPW0 1 << BK23TCR_V_B23RDCPW0
+#define BK23TCR_M_B23RDCPW0 (1 << BK23TCR_V_B23RDCPW0)
#define BK23TCR_V_B23RDCPW1 4
-#define BK23TCR_M_B23RDCPW1 1 << BK23TCR_V_B23RDCPW1
+#define BK23TCR_M_B23RDCPW1 (1 << BK23TCR_V_B23RDCPW1)
#define BK23TCR_V_MA23RDDLY 5
-#define BK23TCR_M_MA23RDDLY 1 << BK23TCR_V_MA23RDDLY
+#define BK23TCR_M_MA23RDDLY (1 << BK23TCR_V_MA23RDDLY)
#define BK23TCR_V_B23CPRE 6
-#define BK23TCR_M_B23CPRE 1 << BK23TCR_V_B23CPRE
+#define BK23TCR_M_B23CPRE (1 << BK23TCR_V_B23CPRE)
#define BK23TCR_V_B23RTMA 7
-#define BK23TCR_M_B23RTMA 1 << BK23TCR_V_B23RTMA
+#define BK23TCR_M_B23RTMA (1 << BK23TCR_V_B23RTMA)
#define BK23TCR_V_B23MATC 8
-#define BK23TCR_M_B23MATC 1 << BK23TCR_V_B23MATC
+#define BK23TCR_M_B23MATC (1 << BK23TCR_V_B23MATC)
#define BK23TCR_V_B23RPRE 9
-#define BK23TCR_M_B23RPRE 0x7 << BK23TCR_V_B23RPRE
+#define BK23TCR_M_B23RPRE (0x7 << BK23TCR_V_B23RPRE)
#define BK23TCR_V_B23RPRE0 9
-#define BK23TCR_M_B23RPRE0 1 << BK23TCR_V_B23RPRE0
+#define BK23TCR_M_B23RPRE0 (1 << BK23TCR_V_B23RPRE0)
#define BK23TCR_V_B23RPRE1 10
-#define BK23TCR_M_B23RPRE1 1 << BK23TCR_V_B23RPRE1
+#define BK23TCR_M_B23RPRE1 (1 << BK23TCR_V_B23RPRE1)
#define BK23TCR_V_B23RPRE2 11
-#define BK23TCR_M_B23RPRE2 1 << BK23TCR_V_B23RPRE2
+#define BK23TCR_M_B23RPRE2 (1 << BK23TCR_V_B23RPRE2)
#define BK23TCR_V_BNK23_ITL 13
-#define BK23TCR_M_BNK23_ITL 1 << BK23TCR_V_BNK23_ITL
+#define BK23TCR_M_BNK23_ITL (1 << BK23TCR_V_BNK23_ITL)
/*
** Bank 2/3 Write CAS Cycle Time
@@ -3619,27 +3619,27 @@
#define DRAMCR_BK4CR_REG 0x208
#define DRAMCR_BK4CR_INIT 0x0000
#define BK4CR_V_B4A 0
-#define BK4CR_M_B4A 0xFF << BK4CR_V_B4A
+#define BK4CR_M_B4A (0xFF << BK4CR_V_B4A)
#define BK4CR_V_B4S 8
-#define BK4CR_M_B4S 0x7 << BK4CR_V_B4S
+#define BK4CR_M_B4S (0x7 << BK4CR_V_B4S)
#define BK4CR_V_B4S0 8
-#define BK4CR_M_B4S0 1 << BK4CR_V_B4S0
+#define BK4CR_M_B4S0 (1 << BK4CR_V_B4S0)
#define BK4CR_V_B4S1 9
-#define BK4CR_M_B4S1 1 << BK4CR_V_B4S1
+#define BK4CR_M_B4S1 (1 << BK4CR_V_B4S1)
#define BK4CR_V_B4S2 10
-#define BK4CR_M_B4S2 1 << BK4CR_V_B4S2
+#define BK4CR_M_B4S2 (1 << BK4CR_V_B4S2)
#define BK4CR_V_BANKEN4 11
-#define BK4CR_M_BANKEN4 1 << BK4CR_V_BANKEN4
+#define BK4CR_M_BANKEN4 (1 << BK4CR_V_BANKEN4)
#define BK4CR_V_ENMDEN4N 12
-#define BK4CR_M_ENMDEN4N 1 << BK4CR_V_ENMDEN4N
+#define BK4CR_M_ENMDEN4N (1 << BK4CR_V_ENMDEN4N)
#define BK4CR_V_COLADR4 13
-#define BK4CR_M_COLADR4 0xE << BK4CR_V_COLADR4
+#define BK4CR_M_COLADR4 (0xE << BK4CR_V_COLADR4)
#define BK4CR_V_COLADR40 13
-#define BK4CR_M_COLADR40 1 << BK4CR_V_COLADR40
+#define BK4CR_M_COLADR40 (1 << BK4CR_V_COLADR40)
#define BK4CR_V_COLADR41 14
-#define BK4CR_M_COLADR41 1 << BK4CR_V_COLADR41
+#define BK4CR_M_COLADR41 (1 << BK4CR_V_COLADR41)
#define BK4CR_V_COLADR42 15
-#define BK4CR_M_COLADR42 1 << BK4CR_V_COLADR42
+#define BK4CR_M_COLADR42 (1 << BK4CR_V_COLADR42)
/*
** Bank 4 DRAM Size
@@ -3680,27 +3680,27 @@
#define DRAMCR_BK5CR_REG 0x209
#define DRAMCR_BK5CR_INIT 0x0000
#define BK5CR_V_B5A 0
-#define BK5CR_M_B5A 0xFF << BK5CR_V_B5A
+#define BK5CR_M_B5A (0xFF << BK5CR_V_B5A)
#define BK5CR_V_B5S 8
-#define BK5CR_M_B5S 0x7 << BK5CR_V_B5S
+#define BK5CR_M_B5S (0x7 << BK5CR_V_B5S)
#define BK5CR_V_B5S0 8
-#define BK5CR_M_B5S0 1 << BK5CR_V_B5S0
+#define BK5CR_M_B5S0 (1 << BK5CR_V_B5S0)
#define BK5CR_V_B5S1 9
-#define BK5CR_M_B5S1 1 << BK5CR_V_B5S1
+#define BK5CR_M_B5S1 (1 << BK5CR_V_B5S1)
#define BK5CR_V_B5S2 10
-#define BK5CR_M_B5S2 1 << BK5CR_V_B5S2
+#define BK5CR_M_B5S2 (1 << BK5CR_V_B5S2)
#define BK5CR_V_BANKEN5 11
-#define BK5CR_M_BANKEN5 1 << BK5CR_V_BANKEN5
+#define BK5CR_M_BANKEN5 (1 << BK5CR_V_BANKEN5)
#define BK5CR_V_ENMDEN5N 12
-#define BK5CR_M_ENMDEN5N 1 << BK5CR_V_ENMDEN5N
+#define BK5CR_M_ENMDEN5N (1 << BK5CR_V_ENMDEN5N)
#define BK5CR_V_COLADR5 13
-#define BK5CR_M_COLADR5 0xE << BK5CR_V_COLADR5
+#define BK5CR_M_COLADR5 (0xE << BK5CR_V_COLADR5)
#define BK5CR_V_COLADR50 13
-#define BK5CR_M_COLADR50 1 << BK5CR_V_COLADR50
+#define BK5CR_M_COLADR50 (1 << BK5CR_V_COLADR50)
#define BK5CR_V_COLADR51 14
-#define BK5CR_M_COLADR51 1 << BK5CR_V_COLADR51
+#define BK5CR_M_COLADR51 (1 << BK5CR_V_COLADR51)
#define BK5CR_V_COLADR52 15
-#define BK5CR_M_COLADR52 1 << BK5CR_V_COLADR52
+#define BK5CR_M_COLADR52 (1 << BK5CR_V_COLADR52)
/*
** Bank 5 DRAM Size
@@ -3749,37 +3749,37 @@
BK45TCR_M_B45CPRE | BK45TCR_M_B45RTMA | \
BK45TCR_M_B45MATC | BK45TCR_M_B45RPRE )
#define BK45TCR_V_B45WRCPW 0
-#define BK45TCR_M_B45WRCPW 0x3 << BK45TCR_V_B45WRCPW
+#define BK45TCR_M_B45WRCPW (0x3 << BK45TCR_V_B45WRCPW)
#define BK45TCR_V_B45WRCPW0 0
-#define BK45TCR_M_B45WRCPW0 1 << BK45TCR_V_B45WRCPW0
+#define BK45TCR_M_B45WRCPW0 (1 << BK45TCR_V_B45WRCPW0)
#define BK45TCR_V_B45WRCPW1 1
-#define BK45TCR_M_B45WRCPW1 1 << BK45TCR_V_B45WRCPW1
+#define BK45TCR_M_B45WRCPW1 (1 << BK45TCR_V_B45WRCPW1)
#define BK45TCR_V_MA45WRDLY 2
-#define BK45TCR_M_MA45WRDLY 1 << BK45TCR_V_MA45WRDLY
+#define BK45TCR_M_MA45WRDLY (1 << BK45TCR_V_MA45WRDLY)
#define BK45TCR_V_B45RDCPW 3
-#define BK45TCR_M_B45RDCPW 0x3 << BK45TCR_V_B45RDCPW
+#define BK45TCR_M_B45RDCPW (0x3 << BK45TCR_V_B45RDCPW)
#define BK45TCR_V_B45RDCPW0 3
-#define BK45TCR_M_B45RDCPW0 1 << BK45TCR_V_B45RDCPW0
+#define BK45TCR_M_B45RDCPW0 (1 << BK45TCR_V_B45RDCPW0)
#define BK45TCR_V_B45RDCPW1 4
-#define BK45TCR_M_B45RDCPW1 1 << BK45TCR_V_B45RDCPW1
+#define BK45TCR_M_B45RDCPW1 (1 << BK45TCR_V_B45RDCPW1)
#define BK45TCR_V_MA45RDDLY 5
-#define BK45TCR_M_MA45RDDLY 1 << BK45TCR_V_MA45RDDLY
+#define BK45TCR_M_MA45RDDLY (1 << BK45TCR_V_MA45RDDLY)
#define BK45TCR_V_B45CPRE 6
-#define BK45TCR_M_B45CPRE 1 << BK45TCR_V_B45CPRE
+#define BK45TCR_M_B45CPRE (1 << BK45TCR_V_B45CPRE)
#define BK45TCR_V_B45RTMA 7
-#define BK45TCR_M_B45RTMA 1 << BK45TCR_V_B45RTMA
+#define BK45TCR_M_B45RTMA (1 << BK45TCR_V_B45RTMA)
#define BK45TCR_V_B45MATC 8
-#define BK45TCR_M_B45MATC 1 << BK45TCR_V_B45MATC
+#define BK45TCR_M_B45MATC (1 << BK45TCR_V_B45MATC)
#define BK45TCR_V_B45RPRE 9
-#define BK45TCR_M_B45RPRE 0x7 << BK45TCR_V_B45RPRE
+#define BK45TCR_M_B45RPRE (0x7 << BK45TCR_V_B45RPRE)
#define BK45TCR_V_B45RPRE0 9
-#define BK45TCR_M_B45RPRE0 1 << BK45TCR_V_B45RPRE0
+#define BK45TCR_M_B45RPRE0 (1 << BK45TCR_V_B45RPRE0)
#define BK45TCR_V_B45RPRE1 10
-#define BK45TCR_M_B45RPRE1 1 << BK45TCR_V_B45RPRE1
+#define BK45TCR_M_B45RPRE1 (1 << BK45TCR_V_B45RPRE1)
#define BK45TCR_V_B45RPRE2 11
-#define BK45TCR_M_B45RPRE2 1 << BK45TCR_V_B45RPRE2
+#define BK45TCR_M_B45RPRE2 (1 << BK45TCR_V_B45RPRE2)
#define BK45TCR_V_BNK45_ITL 13
-#define BK45TCR_M_BNK45_ITL 1 << BK45TCR_V_BNK45_ITL
+#define BK45TCR_M_BNK45_ITL (1 << BK45TCR_V_BNK45_ITL)
/*
** Bank 4/5 Write CAS Cycle Time
@@ -3831,37 +3831,37 @@
#define DRAMCR_DRAMCR1_REG 0x20B
#define DRAMCR_DRAMCR1_INIT ( DRAMCR1_M_XWITDOFFR | DRAMCR1_M_XWITDOFFW )
#define DRAMCR1_V_SIXRASEN 0
-#define DRAMCR1_M_SIXRASEN 1 << DRAMCR1_V_SIXRASEN
+#define DRAMCR1_M_SIXRASEN (1 << DRAMCR1_V_SIXRASEN)
#define DRAMCR1_V_BRSTWREN 3
-#define DRAMCR1_M_BRSTWREN 1 << DRAMCR1_V_BRSTWREN
+#define DRAMCR1_M_BRSTWREN (1 << DRAMCR1_V_BRSTWREN)
#define DRAMCR1_V_PS 4
-#define DRAMCR1_M_PS 0x7 << DRAMCR1_V_PS
+#define DRAMCR1_M_PS (0x7 << DRAMCR1_V_PS)
#define DRAMCR1_V_PS0 4
-#define DRAMCR1_M_PS0 1 << DRAMCR1_V_PS0
+#define DRAMCR1_M_PS0 (1 << DRAMCR1_V_PS0)
#define DRAMCR1_V_PS1 5
-#define DRAMCR1_M_PS1 1 << DRAMCR1_V_PS1
+#define DRAMCR1_M_PS1 (1 << DRAMCR1_V_PS1)
#define DRAMCR1_V_PS2 6
-#define DRAMCR1_M_PS2 1 << DRAMCR1_V_PS2
+#define DRAMCR1_M_PS2 (1 << DRAMCR1_V_PS2)
#define DRAMCR1_V_FSTPHDEC 7
-#define DRAMCR1_M_FSTPHDEC 1 << DRAMCR1_V_FSTPHDEC
+#define DRAMCR1_M_FSTPHDEC (1 << DRAMCR1_V_FSTPHDEC)
#define DRAMCR1_V_RONLYRF 9
-#define DRAMCR1_M_RONLYRF 1 << DRAMCR1_V_RONLYRF
+#define DRAMCR1_M_RONLYRF (1 << DRAMCR1_V_RONLYRF)
#define DRAMCR1_V_RFRPRE 10
-#define DRAMCR1_M_RFRPRE 0x3 << DRAMCR1_V_RFRPRE
+#define DRAMCR1_M_RFRPRE (0x3 << DRAMCR1_V_RFRPRE)
#define DRAMCR1_V_RFRPRE0 10
-#define DRAMCR1_M_RFRPRE0 1 << DRAMCR1_V_RFRPRE0
+#define DRAMCR1_M_RFRPRE0 (1 << DRAMCR1_V_RFRPRE0)
#define DRAMCR1_V_RFRPRE1 11
-#define DRAMCR1_M_RFRPRE1 1 << DRAMCR1_V_RFRPRE1
+#define DRAMCR1_M_RFRPRE1 (1 << DRAMCR1_V_RFRPRE1)
#define DRAMCR1_V_RFRPW 12
-#define DRAMCR1_M_RFRPW 0x3 << DRAMCR1_V_RFRPW
+#define DRAMCR1_M_RFRPW (0x3 << DRAMCR1_V_RFRPW)
#define DRAMCR1_V_RFRPW0 12
-#define DRAMCR1_M_RFRPW0 1 << DRAMCR1_V_RFRPW0
+#define DRAMCR1_M_RFRPW0 (1 << DRAMCR1_V_RFRPW0)
#define DRAMCR1_V_RFRPW1 13
-#define DRAMCR1_M_RFRPW1 1 << DRAMCR1_V_RFRPW1
+#define DRAMCR1_M_RFRPW1 (1 << DRAMCR1_V_RFRPW1)
#define DRAMCR1_V_XWITDOFFR 14
-#define DRAMCR1_M_XWITDOFFR 1 << DRAMCR1_V_XWITDOFFR
+#define DRAMCR1_M_XWITDOFFR (1 << DRAMCR1_V_XWITDOFFR)
#define DRAMCR1_V_XWITDOFFW 15
-#define DRAMCR1_M_XWITDOFFW 1 << DRAMCR1_V_XWITDOFFW
+#define DRAMCR1_M_XWITDOFFW (1 << DRAMCR1_V_XWITDOFFW)
/*
** DRAM Page Size
@@ -3908,19 +3908,19 @@
#define DRAMCR_DRAMCR2_REG 0x20C
#define DRAMCR_DRAMCR2_INIT 0x0000
#define DRAMCR2_V_ENPARADRL 9
-#define DRAMCR2_M_ENPARADRL 1 << DRAMCR2_V_ENPARADRL
+#define DRAMCR2_M_ENPARADRL (1 << DRAMCR2_V_ENPARADRL)
#define DRAMCR2_V_ENPARCK0 10
-#define DRAMCR2_M_ENPARCK0 1 << DRAMCR2_V_ENPARCK0
+#define DRAMCR2_M_ENPARCK0 (1 << DRAMCR2_V_ENPARCK0)
#define DRAMCR2_V_ENPARCK1 11
-#define DRAMCR2_M_ENPARCK1 1 << DRAMCR2_V_ENPARCK1
+#define DRAMCR2_M_ENPARCK1 (1 << DRAMCR2_V_ENPARCK1)
#define DRAMCR2_V_ENPARCK2 12
-#define DRAMCR2_M_ENPARCK2 1 << DRAMCR2_V_ENPARCK2
+#define DRAMCR2_M_ENPARCK2 (1 << DRAMCR2_V_ENPARCK2)
#define DRAMCR2_V_ENPARCK3 13
-#define DRAMCR2_M_ENPARCK3 1 << DRAMCR2_V_ENPARCK3
+#define DRAMCR2_M_ENPARCK3 (1 << DRAMCR2_V_ENPARCK3)
#define DRAMCR2_V_ENPARCK4 14
-#define DRAMCR2_M_ENPARCK4 1 << DRAMCR2_V_ENPARCK4
+#define DRAMCR2_M_ENPARCK4 (1 << DRAMCR2_V_ENPARCK4)
#define DRAMCR2_V_ENPARCK5 15
-#define DRAMCR2_M_ENPARCK5 1 << DRAMCR2_V_ENPARCK5
+#define DRAMCR2_M_ENPARCK5 (1 << DRAMCR2_V_ENPARCK5)
/*
**
@@ -3954,45 +3954,45 @@
DRAMCR3_M_RAS2DRV2 | DRAMCR3_M_RAS3DRV0 | \
DRAMCR3_M_RAS3DRV1 | DRAMCR3_M_RAS3DRV2 )
#define DRAMCR3_V_RAS0DRV 0
-#define DRAMCR3_M_RAS0DRV 0xF << DRAMCR3_V_RAS0DRV
+#define DRAMCR3_M_RAS0DRV (0xF << DRAMCR3_V_RAS0DRV)
#define DRAMCR3_V_RAS0DRV0 0
-#define DRAMCR3_M_RAS0DRV0 1 << DRAMCR3_V_RAS0DRV0
+#define DRAMCR3_M_RAS0DRV0 (1 << DRAMCR3_V_RAS0DRV0)
#define DRAMCR3_V_RAS0DRV1 1
-#define DRAMCR3_M_RAS0DRV1 1 << DRAMCR3_V_RAS0DRV1
+#define DRAMCR3_M_RAS0DRV1 (1 << DRAMCR3_V_RAS0DRV1)
#define DRAMCR3_V_RAS0DRV2 2
-#define DRAMCR3_M_RAS0DRV2 1 << DRAMCR3_V_RAS0DRV2
+#define DRAMCR3_M_RAS0DRV2 (1 << DRAMCR3_V_RAS0DRV2)
#define DRAMCR3_V_RAS0DRV3 3
-#define DRAMCR3_M_RAS0DRV3 1 << DRAMCR3_V_RAS0DRV3
+#define DRAMCR3_M_RAS0DRV3 (1 << DRAMCR3_V_RAS0DRV3)
#define DRAMCR3_V_RAS1DRV 4
-#define DRAMCR3_M_RAS1DRV 0xF << DRAMCR3_V_RAS1DRV
+#define DRAMCR3_M_RAS1DRV (0xF << DRAMCR3_V_RAS1DRV)
#define DRAMCR3_V_RAS1DRV0 4
-#define DRAMCR3_M_RAS1DRV0 1 << DRAMCR3_V_RAS1DRV0
+#define DRAMCR3_M_RAS1DRV0 (1 << DRAMCR3_V_RAS1DRV0)
#define DRAMCR3_V_RAS1DRV1 5
-#define DRAMCR3_M_RAS1DRV1 1 << DRAMCR3_V_RAS1DRV1
+#define DRAMCR3_M_RAS1DRV1 (1 << DRAMCR3_V_RAS1DRV1)
#define DRAMCR3_V_RAS1DRV2 6
-#define DRAMCR3_M_RAS1DRV2 1 << DRAMCR3_V_RAS1DRV2
+#define DRAMCR3_M_RAS1DRV2 (1 << DRAMCR3_V_RAS1DRV2)
#define DRAMCR3_V_RAS1DRV3 7
-#define DRAMCR3_M_RAS1DRV3 1 << DRAMCR3_V_RAS1DRV3
+#define DRAMCR3_M_RAS1DRV3 (1 << DRAMCR3_V_RAS1DRV3)
#define DRAMCR3_V_RAS2DRV 8
-#define DRAMCR3_M_RAS2DRV 0xF << DRAMCR3_V_RAS2DRV
+#define DRAMCR3_M_RAS2DRV (0xF << DRAMCR3_V_RAS2DRV)
#define DRAMCR3_V_RAS2DRV0 8
-#define DRAMCR3_M_RAS2DRV0 1 << DRAMCR3_V_RAS2DRV0
+#define DRAMCR3_M_RAS2DRV0 (1 << DRAMCR3_V_RAS2DRV0)
#define DRAMCR3_V_RAS2DRV1 9
-#define DRAMCR3_M_RAS2DRV1 1 << DRAMCR3_V_RAS2DRV1
+#define DRAMCR3_M_RAS2DRV1 (1 << DRAMCR3_V_RAS2DRV1)
#define DRAMCR3_V_RAS2DRV2 10
-#define DRAMCR3_M_RAS2DRV2 1 << DRAMCR3_V_RAS2DRV2
+#define DRAMCR3_M_RAS2DRV2 (1 << DRAMCR3_V_RAS2DRV2)
#define DRAMCR3_V_RAS2DRV3 11
-#define DRAMCR3_M_RAS2DRV3 1 << DRAMCR3_V_RAS2DRV3
+#define DRAMCR3_M_RAS2DRV3 (1 << DRAMCR3_V_RAS2DRV3)
#define DRAMCR3_V_RAS3DRV 12
-#define DRAMCR3_M_RAS3DRV 0xF << DRAMCR3_V_RAS3DRV
+#define DRAMCR3_M_RAS3DRV (0xF << DRAMCR3_V_RAS3DRV)
#define DRAMCR3_V_RAS3DRV0 12
-#define DRAMCR3_M_RAS3DRV0 1 << DRAMCR3_V_RAS3DRV0
+#define DRAMCR3_M_RAS3DRV0 (1 << DRAMCR3_V_RAS3DRV0)
#define DRAMCR3_V_RAS3DRV1 13
-#define DRAMCR3_M_RAS3DRV1 1 << DRAMCR3_V_RAS3DRV1
+#define DRAMCR3_M_RAS3DRV1 (1 << DRAMCR3_V_RAS3DRV1)
#define DRAMCR3_V_RAS3DRV2 14
-#define DRAMCR3_M_RAS3DRV2 1 << DRAMCR3_V_RAS3DRV2
+#define DRAMCR3_M_RAS3DRV2 (1 << DRAMCR3_V_RAS3DRV2)
#define DRAMCR3_V_RAS3DRV3 15
-#define DRAMCR3_M_RAS3DRV3 1 << DRAMCR3_V_RAS3DRV3
+#define DRAMCR3_M_RAS3DRV3 (1 << DRAMCR3_V_RAS3DRV3)
/*
** Driving Strength of RAS0# Output (mA)
@@ -4049,35 +4049,35 @@
DRAMCR4_M_CASBDRV0 | DRAMCR4_M_CASBDRV1 | \
DRAMCR4_M_CASBDRV2 )
#define DRAMCR4_V_MADRV 0
-#define DRAMCR4_M_MADRV 0xF << DRAMCR4_V_MADRV
+#define DRAMCR4_M_MADRV (0xF << DRAMCR4_V_MADRV)
#define DRAMCR4_V_MADRV0 0
-#define DRAMCR4_M_MADRV0 1 << DRAMCR4_V_MADRV0
+#define DRAMCR4_M_MADRV0 (1 << DRAMCR4_V_MADRV0)
#define DRAMCR4_V_MADRV1 1
-#define DRAMCR4_M_MADRV1 1 << DRAMCR4_V_MADRV1
+#define DRAMCR4_M_MADRV1 (1 << DRAMCR4_V_MADRV1)
#define DRAMCR4_V_MADRV2 2
-#define DRAMCR4_M_MADRV2 1 << DRAMCR4_V_MADRV2
+#define DRAMCR4_M_MADRV2 (1 << DRAMCR4_V_MADRV2)
#define DRAMCR4_V_MADRV3 3
-#define DRAMCR4_M_MADRV3 1 << DRAMCR4_V_MADRV3
+#define DRAMCR4_M_MADRV3 (1 << DRAMCR4_V_MADRV3)
#define DRAMCR4_V_CASADRV 4
-#define DRAMCR4_M_CASADRV 0xF << DRAMCR4_V_CASADRV
+#define DRAMCR4_M_CASADRV (0xF << DRAMCR4_V_CASADRV)
#define DRAMCR4_V_CASADRV0 4
-#define DRAMCR4_M_CASADRV0 1 << DRAMCR4_V_CASADRV0
+#define DRAMCR4_M_CASADRV0 (1 << DRAMCR4_V_CASADRV0)
#define DRAMCR4_V_CASADRV1 5
-#define DRAMCR4_M_CASADRV1 1 << DRAMCR4_V_CASADRV1
+#define DRAMCR4_M_CASADRV1 (1 << DRAMCR4_V_CASADRV1)
#define DRAMCR4_V_CASADRV2 6
-#define DRAMCR4_M_CASADRV2 1 << DRAMCR4_V_CASADRV2
+#define DRAMCR4_M_CASADRV2 (1 << DRAMCR4_V_CASADRV2)
#define DRAMCR4_V_CASADRV3 7
-#define DRAMCR4_M_CASADRV3 1 << DRAMCR4_V_CASADRV3
+#define DRAMCR4_M_CASADRV3 (1 << DRAMCR4_V_CASADRV3)
#define DRAMCR4_V_CASBDRV 8
-#define DRAMCR4_M_CASBDRV 0xF << DRAMCR4_V_CASBDRV
+#define DRAMCR4_M_CASBDRV (0xF << DRAMCR4_V_CASBDRV)
#define DRAMCR4_V_CASBDRV0 8
-#define DRAMCR4_M_CASBDRV0 1 << DRAMCR4_V_CASBDRV0
+#define DRAMCR4_M_CASBDRV0 (1 << DRAMCR4_V_CASBDRV0)
#define DRAMCR4_V_CASBDRV1 9
-#define DRAMCR4_M_CASBDRV1 1 << DRAMCR4_V_CASBDRV1
+#define DRAMCR4_M_CASBDRV1 (1 << DRAMCR4_V_CASBDRV1)
#define DRAMCR4_V_CASBDRV2 10
-#define DRAMCR4_M_CASBDRV2 1 << DRAMCR4_V_CASBDRV2
+#define DRAMCR4_M_CASBDRV2 (1 << DRAMCR4_V_CASBDRV2)
#define DRAMCR4_V_CASBDRV3 11
-#define DRAMCR4_M_CASBDRV3 1 << DRAMCR4_V_CASBDRV3
+#define DRAMCR4_M_CASBDRV3 (1 << DRAMCR4_V_CASBDRV3)
/*
** Driving Strength of MA Output (mA)
@@ -4119,19 +4119,19 @@
#define DRAMCR_DRAMCR5_REG 0x20F
#define DRAMCR_DRAMCR5_INIT 0x0000
#define DRAMCR5_V_FLASHENB 0
-#define DRAMCR5_M_FLASHENB 1 << DRAMCR5_V_FLASHENB
+#define DRAMCR5_M_FLASHENB (1 << DRAMCR5_V_FLASHENB)
#define DRAMCR5_V_ENC0ROMCS 10
-#define DRAMCR5_M_ENC0ROMCS 1 << DRAMCR5_V_ENC0ROMCS
+#define DRAMCR5_M_ENC0ROMCS (1 << DRAMCR5_V_ENC0ROMCS)
#define DRAMCR5_V_ENC8ROMCS 11
-#define DRAMCR5_M_ENC8ROMCS 1 << DRAMCR5_V_ENC8ROMCS
+#define DRAMCR5_M_ENC8ROMCS (1 << DRAMCR5_V_ENC8ROMCS)
#define DRAMCR5_V_END0ROMCS 12
-#define DRAMCR5_M_END0ROMCS 1 << DRAMCR5_V_ENC0ROMCS
+#define DRAMCR5_M_END0ROMCS (1 << DRAMCR5_V_ENC0ROMCS)
#define DRAMCR5_V_END8ROMCS 13
-#define DRAMCR5_M_END8ROMCS 1 << DRAMCR5_V_ENC8ROMCS
+#define DRAMCR5_M_END8ROMCS (1 << DRAMCR5_V_ENC8ROMCS)
#define DRAMCR5_V_ENE0ROMCS 14
-#define DRAMCR5_M_ENE0ROMCS 1 << DRAMCR5_V_ENC0ROMCS
+#define DRAMCR5_M_ENE0ROMCS (1 << DRAMCR5_V_ENC0ROMCS)
#define DRAMCR5_V_ENE8ROMCS 15
-#define DRAMCR5_M_ENE8ROMCS 1 << DRAMCR5_V_ENC8ROMCS
+#define DRAMCR5_M_ENE8ROMCS (1 << DRAMCR5_V_ENC8ROMCS)
/*
** Cache Controller Registers
@@ -4159,29 +4159,29 @@
*/
#define CCR_CCR1_REG 0x400
#define CCR1_V_L2CST 0
-#define CCR1_M_L2CST 0xF << CCR1_V_L2CST
+#define CCR1_M_L2CST (0xF << CCR1_V_L2CST)
#define CCR1_V_L2CST0 0
-#define CCR1_M_L2CST0 1 << CCR1_V_L2CST0
+#define CCR1_M_L2CST0 (1 << CCR1_V_L2CST0)
#define CCR1_V_L2CST1 1
-#define CCR1_M_L2CST1 1 << CCR1_V_L2CST1
+#define CCR1_M_L2CST1 (1 << CCR1_V_L2CST1)
#define CCR1_V_L2CST2 2
-#define CCR1_M_L2CST2 1 << CCR1_V_L2CST2
+#define CCR1_M_L2CST2 (1 << CCR1_V_L2CST2)
#define CCR1_V_L2CST3 3
-#define CCR1_M_L2CST3 1 << CCR1_V_L2CST3
+#define CCR1_M_L2CST3 (1 << CCR1_V_L2CST3)
#define CCR1_V_CSIZE 4
-#define CCR1_M_CSIZE 0xF << CCR1_V_CSIZE
+#define CCR1_M_CSIZE (0xF << CCR1_V_CSIZE)
#define CCR1_V_CSIZE0 4
-#define CCR1_M_CSIZE0 1 << CCR1_V_CSIZE0
+#define CCR1_M_CSIZE0 (1 << CCR1_V_CSIZE0)
#define CCR1_V_CSIZE1 5
-#define CCR1_M_CSIZE1 1 << CCR1_V_CSIZE1
+#define CCR1_M_CSIZE1 (1 << CCR1_V_CSIZE1)
#define CCR1_V_CSIZE2 6
-#define CCR1_M_CSIZE2 1 << CCR1_V_CSIZE2
+#define CCR1_M_CSIZE2 (1 << CCR1_V_CSIZE2)
#define CCR1_V_CSIZE3 7
-#define CCR1_M_CSIZE3 1 << CCR1_V_CSIZE3
+#define CCR1_M_CSIZE3 (1 << CCR1_V_CSIZE3)
#define CCR1_V_L1WB 8
-#define CCR1_M_L1WB 1 << CCR1_V_L1WB
+#define CCR1_M_L1WB (1 << CCR1_V_L1WB)
#define CCR1_V_WPL2KEN 9
-#define CCR1_M_WPL2KEN 1 << CCR1_V_WPL2KEN
+#define CCR1_M_WPL2KEN (1 << CCR1_V_WPL2KEN)
/*
** Level 2 Cache Status
@@ -4219,13 +4219,13 @@
*/
#define CCR_CCR2_REG 0x401
#define CCR2_V_TWIDTH 0
-#define CCR2_M_TWIDTH 1 << CCR2_V_TWIDTH
+#define CCR2_M_TWIDTH (1 << CCR2_V_TWIDTH)
#define CCR2_V_DTYEN 1
-#define CCR2_M_DTYEN 1 << CCR2_V_DTYEN
+#define CCR2_M_DTYEN (1 << CCR2_V_DTYEN)
#define CCR2_V_DRTWEN 2
-#define CCR2_M_DRTWEN 1 << CCR2_V_DRTWEN
+#define CCR2_M_DRTWEN (1 << CCR2_V_DRTWEN)
#define CCR2_V_EHITEN 7
-#define CCR2_M_EHITEN 1 << CCR2_V_EHITEN
+#define CCR2_M_EHITEN (1 << CCR2_V_EHITEN)
/*
**
@@ -4248,33 +4248,33 @@
*/
#define CCR_CCR3_REG 0x402
#define CCR3_V_RDL 0
-#define CCR3_M_RDL 0x3 << CCR3_V_RDL
+#define CCR3_M_RDL (0x3 << CCR3_V_RDL)
#define CCR3_V_RDL0 0
-#define CCR3_M_RDL0 1 << CCR3_V_RDL0
+#define CCR3_M_RDL0 (1 << CCR3_V_RDL0)
#define CCR3_V_RDL1 2
-#define CCR3_M_RDL1 1 << CCR3_V_RDL1
+#define CCR3_M_RDL1 (1 << CCR3_V_RDL1)
#define CCR3_V_RDB2T 3
-#define CCR3_M_RDB2T 1 << CCR3_V_RDB2T
+#define CCR3_M_RDB2T (1 << CCR3_V_RDB2T)
#define CCR3_V_WRL 3
-#define CCR3_M_WRL 0x3 << CCR3_V_WRL
+#define CCR3_M_WRL (0x3 << CCR3_V_WRL)
#define CCR3_V_WRL0 3
-#define CCR3_M_WRL0 1 << CCR3_V_WRL0
+#define CCR3_M_WRL0 (1 << CCR3_V_WRL0)
#define CCR3_V_WRL1 4
-#define CCR3_M_WRL1 1 << CCR3_V_WRL1
+#define CCR3_M_WRL1 (1 << CCR3_V_WRL1)
#define CCR3_V_WRB2T 5
-#define CCR3_M_WRB2T 1 << CCR3_V_WRB2T
+#define CCR3_M_WRB2T (1 << CCR3_V_WRB2T)
#define CCR3_V_WRTEG 6
-#define CCR3_M_WRTEG 0x3 << CCR3_V_WRTEG
+#define CCR3_M_WRTEG (0x3 << CCR3_V_WRTEG)
#define CCR3_V_WRTEG0 6
-#define CCR3_M_WRTEG0 1 << CCR3_V_WRTEG0
+#define CCR3_M_WRTEG0 (1 << CCR3_V_WRTEG0)
#define CCR3_V_WRTEG1 7
-#define CCR3_M_WRTEG1 1 << CCR3_V_WRTEG1
+#define CCR3_M_WRTEG1 (1 << CCR3_V_WRTEG1)
#define CCR3_V_RDTEG 8
-#define CCR3_M_RDTEG 0x3 << CCR3_V_RDTEG
+#define CCR3_M_RDTEG (0x3 << CCR3_V_RDTEG)
#define CCR3_V_RDTEG0 8
-#define CCR3_M_RDTEG0 1 << CCR3_V_RDTEG0
+#define CCR3_M_RDTEG0 (1 << CCR3_V_RDTEG0)
#define CCR3_V_RDTEG1 9
-#define CCR3_M_RDTEG1 1 << CCR3_V_RDTEG1
+#define CCR3_M_RDTEG1 (1 << CCR3_V_RDTEG1)
/*
** CPU Cache Read Lead-off Cycles
@@ -4317,17 +4317,17 @@
*/
#define CCR_CCR4_REG 0x403
#define CCR4_V_TAGCK 0
-#define CCR4_M_TAGCK 0x3 << CCR4_V_TAGCK
+#define CCR4_M_TAGCK (0x3 << CCR4_V_TAGCK)
#define CCR4_V_TAGCK0 0
-#define CCR4_M_TAGCK0 1 << CCR4_V_TAGCK0
+#define CCR4_M_TAGCK0 (1 << CCR4_V_TAGCK0)
#define CCR4_V_TAGCK1 1
-#define CCR4_M_TAGCK1 1 << CCR4_V_TAGCK1
+#define CCR4_M_TAGCK1 (1 << CCR4_V_TAGCK1)
#define CCR4_V_DRTWETR 0
-#define CCR4_M_DRTWETR 0x3 << CCR4_V_DRTWETR
+#define CCR4_M_DRTWETR (0x3 << CCR4_V_DRTWETR)
#define CCR4_V_DRTWETR0 0
-#define CCR4_M_DRTWETR0 1 << CCR4_V_DRTWETR0
+#define CCR4_M_DRTWETR0 (1 << CCR4_V_DRTWETR0)
#define CCR4_V_DRTWETR1 1
-#define CCR4_M_DRTWETR1 1 << CCR4_V_DRTWETR1
+#define CCR4_M_DRTWETR1 (1 << CCR4_V_DRTWETR1)
/*
** TAG RAM Timing Checking Point
@@ -4357,7 +4357,7 @@
#define CCR_GCR1_REG 0x700
#define CCR_GCR1_INIT 0x0000
#define GCR1_V_CPUHITMWS 0
-#define GCR1_M_CPUHITMWS 1 << GCR1_V_CPUHITMWS
+#define GCR1_M_CPUHITMWS (1 << GCR1_V_CPUHITMWS)
/****************************************************
** SEQUOIA-2 **
@@ -4386,31 +4386,31 @@
#define SEQ2_ATMCR_INIT ( SYSDIV_4 | IDERDYDLY_2FS1XCLK | B2BD_3 | \
ATMCR1_M_ATREFDIS | ATMCR1_M_HIDREFEN )
#define ATMCR1_V_SYSDIV 0
-#define ATMCR1_M_SYSDIV 0x7 << ATMCR1_V_SYSDIV
+#define ATMCR1_M_SYSDIV (0x7 << ATMCR1_V_SYSDIV)
#define ATMCR1_V_SYSDIV0 0
-#define ATMCR1_M_SYSDIV0 1 << ATMCR1_V_SYSDIV0
+#define ATMCR1_M_SYSDIV0 (1 << ATMCR1_V_SYSDIV0)
#define ATMCR1_V_SYSDIV1 1
-#define ATMCR1_M_SYSDIV1 1 << ATMCR1_V_SYSDIV1
+#define ATMCR1_M_SYSDIV1 (1 << ATMCR1_V_SYSDIV1)
#define ATMCR1_V_SYSDIV2 2
-#define ATMCR1_M_SYSDIV2 1 << ATMCR1_V_SYSDIV2
+#define ATMCR1_M_SYSDIV2 (1 << ATMCR1_V_SYSDIV2)
#define ATMCR1_V_IDERDYDLY 4
-#define ATMCR1_M_IDERDYDLY 0x3 << ATMCR1_V_IDERDYDLY
+#define ATMCR1_M_IDERDYDLY (0x3 << ATMCR1_V_IDERDYDLY)
#define ATMCR1_V_IDERDYDLY0 4
-#define ATMCR1_M_IDERDYDLY0 1 << ATMCR1_V_IDERDYDLY0
+#define ATMCR1_M_IDERDYDLY0 (1 << ATMCR1_V_IDERDYDLY0)
#define ATMCR1_V_IDERDYDLY1 5
-#define ATMCR1_M_IDERDYDLY1 1 << ATMCR1_V_IDERDYDLY1
+#define ATMCR1_M_IDERDYDLY1 (1 << ATMCR1_V_IDERDYDLY1)
#define ATMCR1_V_B2BD 6
-#define ATMCR1_M_B2BD 0x3 << ATMCR1_V_B2BD
+#define ATMCR1_M_B2BD (0x3 << ATMCR1_V_B2BD)
#define ATMCR1_V_B2BD0 6
-#define ATMCR1_M_B2BD0 1 << ATMCR1_V_B2BD0
+#define ATMCR1_M_B2BD0 (1 << ATMCR1_V_B2BD0)
#define ATMCR1_V_B2BD1 7
-#define ATMCR1_M_B2BD1 1 << ATMCR1_V_B2BD1
+#define ATMCR1_M_B2BD1 (1 << ATMCR1_V_B2BD1)
#define ATMCR1_V_PARITYEN 9
-#define ATMCR1_M_PARITYEN 1 << ATMCR1_V_PARITYEN
+#define ATMCR1_M_PARITYEN (1 << ATMCR1_V_PARITYEN)
#define ATMCR1_V_ATREFDIS 10
-#define ATMCR1_M_ATREFDIS 1 << ATMCR1_V_ATREFDIS
+#define ATMCR1_M_ATREFDIS (1 << ATMCR1_V_ATREFDIS)
#define ATMCR1_V_HIDREFEN 11
-#define ATMCR1_M_HIDREFEN 1 << ATMCR1_V_HIDREFEN
+#define ATMCR1_M_HIDREFEN (1 << ATMCR1_V_HIDREFEN)
/*
** SYSCLK Divisor Select
@@ -4530,19 +4530,19 @@
#define SEQ2_SEQ2PSR_REG 0x302
#define SEQ2_SEQ2PSR_INIT ( SEQ2PSR_M_DPBUSEN | SEQ2PSR_M_LOCALPINEN )
#define SEQ2PSR_V_DPBUSEN 0
-#define SEQ2PSR_M_DPBUSEN 1 << SEQ2PSR_V_DPBUSEN
+#define SEQ2PSR_M_DPBUSEN (1 << SEQ2PSR_V_DPBUSEN)
#define SEQ2PSR_V_GPIOPINEN 1
-#define SEQ2PSR_M_GPIOPINEN 1 << SEQ2PSR_V_GPIOPINEN
+#define SEQ2PSR_M_GPIOPINEN (1 << SEQ2PSR_V_GPIOPINEN)
#define SEQ2PSR_V_IDEPINEN 4
-#define SEQ2PSR_M_IDEPINEN 1 << SEQ2PSR_V_IDEPINEN
+#define SEQ2PSR_M_IDEPINEN (1 << SEQ2PSR_V_IDEPINEN)
#define SEQ2PSR_V_LOCALPINEN 5
-#define SEQ2PSR_M_LOCALPINEN 1 << SEQ2PSR_V_LOCALPINEN
+#define SEQ2PSR_M_LOCALPINEN (1 << SEQ2PSR_V_LOCALPINEN)
#define SEQ2PSR_V_ATREFADDEN 8
-#define SEQ2PSR_M_ATREFADDEN 1 << SEQ2PSR_V_ATREFADDEN
+#define SEQ2PSR_M_ATREFADDEN (1 << SEQ2PSR_V_ATREFADDEN)
#define SEQ2PSR_V_IDECMDEN 14
-#define SEQ2PSR_M_IDECMDEN 1 << SEQ2PSR_V_IDECMDEN
+#define SEQ2PSR_M_IDECMDEN (1 << SEQ2PSR_V_IDECMDEN)
#define SEQ2PSR_V_SQ2TYPESEL 15
-#define SEQ2PSR_M_SQ2TYPESEL 1 << SEQ2PSR_V_SQ2TYPESEL
+#define SEQ2PSR_M_SQ2TYPESEL (1 << SEQ2PSR_V_SQ2TYPESEL)
/*
**
@@ -4560,13 +4560,13 @@
#define SEQ2_MCLKCR_REG 0x303
#define SEQ2_MCLKCR_INIT 0x0000
#define MCLKCR_V_ATMODCLKEN 0
-#define MCLKCR_M_ATMODCLKEN 1 << MCLKCR_V_ATMODCLKEN
+#define MCLKCR_M_ATMODCLKEN (1 << MCLKCR_V_ATMODCLKEN)
#define MCLKCR_V_SYNCTMREN 3
-#define MCLKCR_M_SYNCTMREN 1 << MCLKCR_V_SYNCTMREN
+#define MCLKCR_M_SYNCTMREN (1 << MCLKCR_V_SYNCTMREN)
#define MCLKCR_V_TMRCLKDIS 4
-#define MCLKCR_M_TMRCLKDIS 1 << MCLKCR_V_TMRCLKDIS
+#define MCLKCR_M_TMRCLKDIS (1 << MCLKCR_V_TMRCLKDIS)
#define MCLKCR_V_SYSCLKDIS 5
-#define MCLKCR_M_SYSCLKDIS 1 << MCLKCR_V_SYSCLKDIS
+#define MCLKCR_M_SYSCLKDIS (1 << MCLKCR_V_SYSCLKDIS)
/*
**
@@ -4582,25 +4582,25 @@
#define SEQ2_OGPIOCR_REG 0x304
#define SEQ2_OGPIOCR_INIT OGPIOCR_M_GPIODIR
#define OOGPIOCR_V_GPIODATA 8
-#define OGPIOCR_M_GPIODATA 0xF << OGPIOCR_V_GPIODATA
+#define OGPIOCR_M_GPIODATA (0xF << OGPIOCR_V_GPIODATA)
#define OGPIOCR_V_GPIODATA4 8
-#define OGPIOCR_M_GPIODATA4 1 << OGPIOCR_V_GPIODATA4
+#define OGPIOCR_M_GPIODATA4 (1 << OGPIOCR_V_GPIODATA4)
#define OGPIOCR_V_GPIODATA5 9
-#define OGPIOCR_M_GPIODATA5 1 << OGPIOCR_V_GPIODATA5
+#define OGPIOCR_M_GPIODATA5 (1 << OGPIOCR_V_GPIODATA5)
#define OGPIOCR_V_GPIODATA6 10
-#define OGPIOCR_M_GPIODATA6 1 << OGPIOCR_V_GPIODATA6
+#define OGPIOCR_M_GPIODATA6 (1 << OGPIOCR_V_GPIODATA6)
#define OGPIOCR_V_GPIODATA7 11
-#define OGPIOCR_M_GPIODATA7 1 << OGPIOCR_V_GPIODATA7
+#define OGPIOCR_M_GPIODATA7 (1 << OGPIOCR_V_GPIODATA7)
#define OGPIOCR_V_GPIODIR 12
-#define OGPIOCR_M_GPIODIR 0xF << OGPIOCR_V_GPIODIR
+#define OGPIOCR_M_GPIODIR (0xF << OGPIOCR_V_GPIODIR)
#define OGPIOCR_V_GPIODIR4 12
-#define OGPIOCR_M_GPIODIR4 1 << OGPIOCR_V_GPIODIR4
+#define OGPIOCR_M_GPIODIR4 (1 << OGPIOCR_V_GPIODIR4)
#define OGPIOCR_V_GPIODIR5 13
-#define OGPIOCR_M_GPIODIR5 1 << OGPIOCR_V_GPIODIR5
+#define OGPIOCR_M_GPIODIR5 (1 << OGPIOCR_V_GPIODIR5)
#define OGPIOCR_V_GPIODIR6 14
-#define OGPIOCR_M_GPIODIR6 1 << OGPIOCR_V_GPIODIR6
+#define OGPIOCR_M_GPIODIR6 (1 << OGPIOCR_V_GPIODIR6)
#define OGPIOCR_V_GPIODIR7 15
-#define OGPIOCR_M_GPIODIR7 1 << OGPIOCR_V_GPIODIR7
+#define OGPIOCR_M_GPIODIR7 (1 << OGPIOCR_V_GPIODIR7)
/*
**
@@ -4614,7 +4614,7 @@
*/
#define SEQ2_SEQ2IDR_REG 0x310
#define SEQ2IDR_V_S2ID 0
-#define SEQ2IDR_M_S2ID 0xF << SEQ2IDR_V_S2ID
+#define SEQ2IDR_M_S2ID (0xF << SEQ2IDR_V_S2ID)
/*
**
@@ -4629,7 +4629,7 @@
#define SEQ2_MDMACR1_REG 0x330
#define SEQ2_MDMACR1_INIT 0x0000
#define MDMACR1_V_ENCDDMA 8
-#define MDMACR1_M_ENCDDMA 1 << MDMACR1_V_ENCDDMA
+#define MDMACR1_M_ENCDDMA (1 << MDMACR1_V_ENCDDMA)
/*
**
@@ -4653,31 +4653,31 @@
#define SEQ2_MDMACR2_REG 0x331
#define SEQ2_MDMACR2_INIT 0x0000
#define MDMACR2_V_SEL3DMA 0
-#define MDMACR2_M_SEL3DMA 1 << MDMACR2_V_SEL3DMA
+#define MDMACR2_M_SEL3DMA (1 << MDMACR2_V_SEL3DMA)
#define MDMACR2_V_DMA0CHSEL 4
-#define MDMACR2_M_DMA0CHSEL 0x7 << MDMACR2_V_DMA0CHSEL
+#define MDMACR2_M_DMA0CHSEL (0x7 << MDMACR2_V_DMA0CHSEL)
#define MDMACR2_V_DMA0CHSEL0 4
-#define MDMACR2_M_DMA0CHSEL0 1 << MDMACR2_V_DMA0CHSEL0
+#define MDMACR2_M_DMA0CHSEL0 (1 << MDMACR2_V_DMA0CHSEL0)
#define MDMACR2_V_DMA0CHSEL1 5
-#define MDMACR2_M_DMA0CHSEL1 1 << MDMACR2_V_DMA0CHSEL1
+#define MDMACR2_M_DMA0CHSEL1 (1 << MDMACR2_V_DMA0CHSEL1)
#define MDMACR2_V_DMA0CHSEL2 6
-#define MDMACR2_M_DMA0CHSEL2 1 << MDMACR2_V_DMA0CHSEL2
+#define MDMACR2_M_DMA0CHSEL2 (1 << MDMACR2_V_DMA0CHSEL2)
#define MDMACR2_V_DMA1CHSEL 7
-#define MDMACR2_M_DMA1CHSEL 0x7 << MDMACR2_V_DMA1CHSEL
+#define MDMACR2_M_DMA1CHSEL (0x7 << MDMACR2_V_DMA1CHSEL)
#define MDMACR2_V_DMA1CHSEL0 7
-#define MDMACR2_M_DMA1CHSEL0 1 << MDMACR2_V_DMA1CHSEL0
+#define MDMACR2_M_DMA1CHSEL0 (1 << MDMACR2_V_DMA1CHSEL0)
#define MDMACR2_V_DMA1CHSEL1 8
-#define MDMACR2_M_DMA1CHSEL1 1 << MDMACR2_V_DMA1CHSEL1
+#define MDMACR2_M_DMA1CHSEL1 (1 << MDMACR2_V_DMA1CHSEL1)
#define MDMACR2_V_DMA1CHSEL2 9
-#define MDMACR2_M_DMA1CHSEL2 1 << MDMACR2_V_DMA1CHSEL2
+#define MDMACR2_M_DMA1CHSEL2 (1 << MDMACR2_V_DMA1CHSEL2)
#define MDMACR2_V_DMA2CHSEL 12
-#define MDMACR2_M_DMA2CHSEL 0x7 << MDMACR2_V_DMA2CHSEL
+#define MDMACR2_M_DMA2CHSEL (0x7 << MDMACR2_V_DMA2CHSEL)
#define MDMACR2_V_DMA2CHSEL0 12
-#define MDMACR2_M_DMA2CHSEL0 1 << MDMACR2_V_DMA2CHSEL0
+#define MDMACR2_M_DMA2CHSEL0 (1 << MDMACR2_V_DMA2CHSEL0)
#define MDMACR2_V_DMA2CHSEL1 13
-#define MDMACR2_M_DMA2CHSEL1 1 << MDMACR2_V_DMA2CHSEL1
+#define MDMACR2_M_DMA2CHSEL1 (1 << MDMACR2_V_DMA2CHSEL1)
#define MDMACR2_V_DMA2CHSEL2 14
-#define MDMACR2_M_DMA2CHSEL2 1 << MDMACR2_V_DMA2CHSEL2
+#define MDMACR2_M_DMA2CHSEL2 (1 << MDMACR2_V_DMA2CHSEL2)
/*
** DMA Channel 0 Select
@@ -4727,11 +4727,11 @@
#define SEQ2_BBICR_REG 0x340
#define SEQ2_BBICR_INIT 0x0000
#define BBICR_V_ENBINT 0
-#define BBICR_M_ENBINT 1 << BBICR_V_ENBINT
+#define BBICR_M_ENBINT (1 << BBICR_V_ENBINT)
#define BBICR_V_BINTLOCKCLR 1
-#define BBICR_M_BINTLOCKCLR 1 << BBICR_V_BINTLOCKCLR
+#define BBICR_M_BINTLOCKCLR (1 << BBICR_V_BINTLOCKCLR)
#define BBICR_V_BINTLOCKDIS 2
-#define BBICR_M_BINTLOCKDIS 1 << BBICR_V_BINTLOCKDIS
+#define BBICR_M_BINTLOCKDIS (1 << BBICR_V_BINTLOCKDIS)
/*
**
@@ -4765,33 +4765,33 @@
PAIMR_M_PAMSKIRQ12 | PAIMR_M_PAMSKIRQ13 | \
PAIMR_M_PAMSKIRQ14 )
#define PAIMR_V_PAMSKIRQ1 1
-#define PAIMR_M_PAMSKIRQ1 1 << PAIMR_V_PAMSKIRQ1
+#define PAIMR_M_PAMSKIRQ1 (1 << PAIMR_V_PAMSKIRQ1)
#define PAIMR_V_PAMSKIRQ3 3
-#define PAIMR_M_PAMSKIRQ3 1 << PAIMR_V_PAMSKIRQ3
+#define PAIMR_M_PAMSKIRQ3 (1 << PAIMR_V_PAMSKIRQ3)
#define PAIMR_V_PAMSKIRQ4 4
-#define PAIMR_M_PAMSKIRQ4 1 << PAIMR_V_PAMSKIRQ4
+#define PAIMR_M_PAMSKIRQ4 (1 << PAIMR_V_PAMSKIRQ4)
#define PAIMR_V_PAMSKIRQ5 5
-#define PAIMR_M_PAMSKIRQ5 1 << PAIMR_V_PAMSKIRQ5
+#define PAIMR_M_PAMSKIRQ5 (1 << PAIMR_V_PAMSKIRQ5)
#define PAIMR_V_PAMSKIRQ6 6
-#define PAIMR_M_PAMSKIRQ6 1 << PAIMR_V_PAMSKIRQ6
+#define PAIMR_M_PAMSKIRQ6 (1 << PAIMR_V_PAMSKIRQ6)
#define PAIMR_V_PAMSKIRQ7 7
-#define PAIMR_M_PAMSKIRQ7 1 << PAIMR_V_PAMSKIRQ7
+#define PAIMR_M_PAMSKIRQ7 (1 << PAIMR_V_PAMSKIRQ7)
#define PAIMR_V_PAMSKIRQ8 8
-#define PAIMR_M_PAMSKIRQ8 1 << PAIMR_V_PAMSKIRQ8
+#define PAIMR_M_PAMSKIRQ8 (1 << PAIMR_V_PAMSKIRQ8)
#define PAIMR_V_PAMSKIRQ9 9
-#define PAIMR_M_PAMSKIRQ9 1 << PAIMR_V_PAMSKIRQ9
+#define PAIMR_M_PAMSKIRQ9 (1 << PAIMR_V_PAMSKIRQ9)
#define PAIMR_V_PAMSKIRQ10 10
-#define PAIMR_M_PAMSKIRQ10 1 << PAIMR_V_PAMSKIRQ10
+#define PAIMR_M_PAMSKIRQ10 (1 << PAIMR_V_PAMSKIRQ10)
#define PAIMR_V_PAMSKIRQ11 11
-#define PAIMR_M_PAMSKIRQ11 1 << PAIMR_V_PAMSKIRQ11
+#define PAIMR_M_PAMSKIRQ11 (1 << PAIMR_V_PAMSKIRQ11)
#define PAIMR_V_PAMSKIRQ12 12
-#define PAIMR_M_PAMSKIRQ12 1 << PAIMR_V_PAMSKIRQ12
+#define PAIMR_M_PAMSKIRQ12 (1 << PAIMR_V_PAMSKIRQ12)
#define PAIMR_V_PAMSKIRQ13 13
-#define PAIMR_M_PAMSKIRQ13 1 << PAIMR_V_PAMSKIRQ13
+#define PAIMR_M_PAMSKIRQ13 (1 << PAIMR_V_PAMSKIRQ13)
#define PAIMR_V_PAMSKIRQ14 14
-#define PAIMR_M_PAMSKIRQ14 1 << PAIMR_V_PAMSKIRQ14
+#define PAIMR_M_PAMSKIRQ14 (1 << PAIMR_V_PAMSKIRQ14)
#define PAIMR_V_PAMSKIRQ15 15
-#define PAIMR_M_PAMSKIRQ15 1 << PAIMR_V_PAMSKIRQ15
+#define PAIMR_M_PAMSKIRQ15 (1 << PAIMR_V_PAMSKIRQ15)
/*
**
@@ -4820,35 +4820,35 @@
#define SEQ2_PTSIAR_REG 0x351
#define SEQ2_PTSIAR_INIT 0x0000
#define PTSIAR_V_PMIDETBACTV 0
-#define PTSIAR_M_PMIDETBACTV 1 << PTSIAR_V_PMIDETBACTV
+#define PTSIAR_M_PMIDETBACTV (1 << PTSIAR_V_PMIDETBACTV)
#define PTSIAR_V_PMIIRQ1ACTV 1
-#define PTSIAR_M_PMIIRQ1ACTV 1 << PTSIAR_V_PMIIRQ1ACTV
+#define PTSIAR_M_PMIIRQ1ACTV (1 << PTSIAR_V_PMIIRQ1ACTV)
#define PTSIAR_V_PMIIRQ3ACTV 3
-#define PTSIAR_M_PMIIRQ3ACTV 1 << PTSIAR_V_PMIIRQ3ACTV
+#define PTSIAR_M_PMIIRQ3ACTV (1 << PTSIAR_V_PMIIRQ3ACTV)
#define PTSIAR_V_PMIIRQ4ACTV 4
-#define PTSIAR_M_PMIIRQ4ACTV 1 << PTSIAR_V_PMIIRQ4ACTV
+#define PTSIAR_M_PMIIRQ4ACTV (1 << PTSIAR_V_PMIIRQ4ACTV)
#define PTSIAR_V_PMIIRQ5ACTV 5
-#define PTSIAR_M_PMIIRQ5ACTV 1 << PTSIAR_V_PMIIRQ5ACTV
+#define PTSIAR_M_PMIIRQ5ACTV (1 << PTSIAR_V_PMIIRQ5ACTV)
#define PTSIAR_V_PMIIRQ6ACTV 6
-#define PTSIAR_M_PMIIRQ6ACTV 1 << PTSIAR_V_PMIIRQ6ACTV
+#define PTSIAR_M_PMIIRQ6ACTV (1 << PTSIAR_V_PMIIRQ6ACTV)
#define PTSIAR_V_PMIIRQ7ACTV 7
-#define PTSIAR_M_PMIIRQ7ACTV 1 << PTSIAR_V_PMIIRQ7ACTV
+#define PTSIAR_M_PMIIRQ7ACTV (1 << PTSIAR_V_PMIIRQ7ACTV)
#define PTSIAR_V_PMIIRQ8ACTV 8
-#define PTSIAR_M_PMIIRQ8ACTV 1 << PTSIAR_V_PMIIRQ8ACTV
+#define PTSIAR_M_PMIIRQ8ACTV (1 << PTSIAR_V_PMIIRQ8ACTV)
#define PTSIAR_V_PMIIRQ9ACTV 9
-#define PTSIAR_M_PMIIRQ9ACTV 1 << PTSIAR_V_PMIIRQ9ACTV
+#define PTSIAR_M_PMIIRQ9ACTV (1 << PTSIAR_V_PMIIRQ9ACTV)
#define PTSIAR_V_PMIIRQ10ACTV 10
-#define PTSIAR_M_PMIIRQ10ACTV 1 << PTSIAR_V_PMIIRQ10ACTV
+#define PTSIAR_M_PMIIRQ10ACTV (1 << PTSIAR_V_PMIIRQ10ACTV)
#define PTSIAR_V_PMIIRQ11ACTV 11
-#define PTSIAR_M_PMIIRQ11ACTV 1 << PTSIAR_V_PMIIRQ11ACTV
+#define PTSIAR_M_PMIIRQ11ACTV (1 << PTSIAR_V_PMIIRQ11ACTV)
#define PTSIAR_V_PMIIRQ12ACTV 12
-#define PTSIAR_M_PMIIRQ12ACTV 1 << PTSIAR_V_PMIIRQ12ACTV
+#define PTSIAR_M_PMIIRQ12ACTV (1 << PTSIAR_V_PMIIRQ12ACTV)
#define PTSIAR_V_PMIIRQ13ACTV 13
-#define PTSIAR_M_PMIIRQ13ACTV 1 << PTSIAR_V_PMIIRQ13ACTV
+#define PTSIAR_M_PMIIRQ13ACTV (1 << PTSIAR_V_PMIIRQ13ACTV)
#define PTSIAR_V_PMIIRQ14ACTV 14
-#define PTSIAR_M_PMIIRQ14ACTV 1 << PTSIAR_V_PMIIRQ14ACTV
+#define PTSIAR_M_PMIIRQ14ACTV (1 << PTSIAR_V_PMIIRQ14ACTV)
#define PTSIAR_V_PMIIRQ15ACTV 15
-#define PTSIAR_M_PMIIRQ15ACTV 1 << PTSIAR_V_PMIIRQ15ACTV
+#define PTSIAR_M_PMIIRQ15ACTV (1 << PTSIAR_V_PMIIRQ15ACTV)
/*
**
@@ -4884,35 +4884,35 @@
PTSIMR_M_IMSKIRQ13 | PTSIMR_M_IMSKIRQ14 | \
PTSIMR_M_IMSKIRQ15 )
#define PTSIMR_V_IMSKDETURBO 0
-#define PTSIMR_M_IMSKDETURBO 1 << PTSIMR_V_IMSKDETURBO
+#define PTSIMR_M_IMSKDETURBO (1 << PTSIMR_V_IMSKDETURBO)
#define PTSIMR_V_IMSKIRQ1 1
-#define PTSIMR_M_IMSKIRQ1 1 << PTSIMR_V_IMSKIRQ1
+#define PTSIMR_M_IMSKIRQ1 (1 << PTSIMR_V_IMSKIRQ1)
#define PTSIMR_V_IMSKIRQ3 3
-#define PTSIMR_M_IMSKIRQ3 1 << PTSIMR_V_IMSKIRQ3
+#define PTSIMR_M_IMSKIRQ3 (1 << PTSIMR_V_IMSKIRQ3)
#define PTSIMR_V_IMSKIRQ4 4
-#define PTSIMR_M_IMSKIRQ4 1 << PTSIMR_V_IMSKIRQ4
+#define PTSIMR_M_IMSKIRQ4 (1 << PTSIMR_V_IMSKIRQ4)
#define PTSIMR_V_IMSKIRQ5 5
-#define PTSIMR_M_IMSKIRQ5 1 << PTSIMR_V_IMSKIRQ5
+#define PTSIMR_M_IMSKIRQ5 (1 << PTSIMR_V_IMSKIRQ5)
#define PTSIMR_V_IMSKIRQ6 6
-#define PTSIMR_M_IMSKIRQ6 1 << PTSIMR_V_IMSKIRQ6
+#define PTSIMR_M_IMSKIRQ6 (1 << PTSIMR_V_IMSKIRQ6)
#define PTSIMR_V_IMSKIRQ7 7
-#define PTSIMR_M_IMSKIRQ7 1 << PTSIMR_V_IMSKIRQ7
+#define PTSIMR_M_IMSKIRQ7 (1 << PTSIMR_V_IMSKIRQ7)
#define PTSIMR_V_IMSKIRQ8 8
-#define PTSIMR_M_IMSKIRQ8 1 << PTSIMR_V_IMSKIRQ8
+#define PTSIMR_M_IMSKIRQ8 (1 << PTSIMR_V_IMSKIRQ8)
#define PTSIMR_V_IMSKIRQ9 9
-#define PTSIMR_M_IMSKIRQ9 1 << PTSIMR_V_IMSKIRQ9
+#define PTSIMR_M_IMSKIRQ9 (1 << PTSIMR_V_IMSKIRQ9)
#define PTSIMR_V_IMSKIRQ10 10
-#define PTSIMR_M_IMSKIRQ10 1 << PTSIMR_V_IMSKIRQ10
+#define PTSIMR_M_IMSKIRQ10 (1 << PTSIMR_V_IMSKIRQ10)
#define PTSIMR_V_IMSKIRQ11 11
-#define PTSIMR_M_IMSKIRQ11 1 << PTSIMR_V_IMSKIRQ11
+#define PTSIMR_M_IMSKIRQ11 (1 << PTSIMR_V_IMSKIRQ11)
#define PTSIMR_V_IMSKIRQ12 12
-#define PTSIMR_M_IMSKIRQ12 1 << PTSIMR_V_IMSKIRQ12
+#define PTSIMR_M_IMSKIRQ12 (1 << PTSIMR_V_IMSKIRQ12)
#define PTSIMR_V_IMSKIRQ13 13
-#define PTSIMR_M_IMSKIRQ13 1 << PTSIMR_V_IMSKIRQ13
+#define PTSIMR_M_IMSKIRQ13 (1 << PTSIMR_V_IMSKIRQ13)
#define PTSIMR_V_IMSKIRQ14 14
-#define PTSIMR_M_IMSKIRQ14 1 << PTSIMR_V_IMSKIRQ14
+#define PTSIMR_M_IMSKIRQ14 (1 << PTSIMR_V_IMSKIRQ14)
#define PTSIMR_V_IMSKIRQ15 15
-#define PTSIMR_M_IMSKIRQ15 1 << PTSIMR_V_IMSKIRQ15
+#define PTSIMR_M_IMSKIRQ15 (1 << PTSIMR_V_IMSKIRQ15)
/*
**
@@ -4927,7 +4927,7 @@
#define SEQ2_ISAER_REG 0x353
#define SEQ2_ISAER_INIT ISAER_M_SAMSKIRQ
#define ISAER_V_SAMSKIRQ 0
-#define ISAER_M_SAMSKIRQ 1 << ISAER_V_SAMSKIRQ
+#define ISAER_M_SAMSKIRQ (1 << ISAER_V_SAMSKIRQ)
/*
** Shadow Read Registers
@@ -5001,21 +5001,21 @@
#define ATSR_REG1_REG 0x061
#define ATSR_REG1_INIT REG1_M_PARDIS
#define REG1_V_TMR2EN 0
-#define REG1_M_TMR2EN 1 << REG1_V_TMR2EN
+#define REG1_M_TMR2EN (1 << REG1_V_TMR2EN)
#define REG1_V_SPKREN 1
-#define REG1_M_SPKREN 1 << REG1_V_SPKREN
+#define REG1_M_SPKREN (1 << REG1_V_SPKREN)
#define REG1_V_PARDIS 2
-#define REG1_M_PARDIS 1 << REG1_V_PARDIS
+#define REG1_M_PARDIS (1 << REG1_V_PARDIS)
#define REG1_V_IOCHKDIS 3
-#define REG1_M_IOCHKDIS 1 << REG1_V_IOCHKDIS
+#define REG1_M_IOCHKDIS (1 << REG1_V_IOCHKDIS)
#define REG1_V_REFRTGL 4
-#define REG1_M_REFRTGL 1 << REG1_V_REFRTGL
+#define REG1_M_REFRTGL (1 << REG1_V_REFRTGL)
#define REG1_V_TMR2OUT 5
-#define REG1_M_TMR2OUT 1 << REG1_V_TMR2OUT
+#define REG1_M_TMR2OUT (1 << REG1_V_TMR2OUT)
#define REG1_V_IOCKERR 6
-#define REG1_M_IOCKERR 1 << REG1_V_IOCKERR
+#define REG1_M_IOCKERR (1 << REG1_V_IOCKERR)
#define REG1_V_PARERR 7
-#define REG1_M_PARERR 1 << REG1_V_PARERR
+#define REG1_M_PARERR (1 << REG1_V_PARERR)
/*
**
@@ -5030,9 +5030,9 @@
#define ATSR_REG2_REG 0x070
#define ATSR_REG2_INIT REG2_M_NMIDIS
#define REG2_V_RTCINDX 0
-#define REG2_M_RTCINDX 0x7F << REG2_V_RTCINDX
+#define REG2_M_RTCINDX (0x7F << REG2_V_RTCINDX)
#define REG2_V_NMIDIS 7
-#define REG2_M_NMIDIS 1 << REG2_V_NMIDIS
+#define REG2_M_NMIDIS (1 << REG2_V_NMIDIS)
/*
**
@@ -5049,11 +5049,11 @@
#define ATSR_REG3_REG 0x092
#define ATSR_REG3_INIT 0x0000
#define REG3_V_FSTRST 0
-#define REG3_M_FSTRST 1 << REG3_V_FSTRST
+#define REG3_M_FSTRST (1 << REG3_V_FSTRST)
#define REG3_V_FGATEA20 1
-#define REG3_M_FGATEA20 1 << REG3_V_FGATEA20
+#define REG3_M_FGATEA20 (1 << REG3_V_FGATEA20)
#define REG3_V_SCLOCK1 3
-#define REG3_M_SCLOCK1 1 << REG3_V_SCLOCK1
+#define REG3_M_SCLOCK1 (1 << REG3_V_SCLOCK1)
