Module Name: src
Committed By: jmcneill
Date: Wed Sep 6 18:08:35 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: a9_mpsubr.S
Log Message:
Clear TEX Remap Enable in SCTLR. U-Boot with CONFIG_ARMV8_SWITCH_TO_EL1
sets it since it is RES1 when TTBCR.EAE=1, but we are still using the
short descriptor format and don't currently support TEX remap.
ok skrll@
To generate a diff of this commit:
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/arm/cortex/a9_mpsubr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9_mpsubr.S
diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.49 src/sys/arch/arm/cortex/a9_mpsubr.S:1.50
--- src/sys/arch/arm/cortex/a9_mpsubr.S:1.49 Mon Jul 24 19:37:41 2017
+++ src/sys/arch/arm/cortex/a9_mpsubr.S Wed Sep 6 18:08:35 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: a9_mpsubr.S,v 1.49 2017/07/24 19:37:41 joerg Exp $ */
+/* $NetBSD: a9_mpsubr.S,v 1.50 2017/09/06 18:08:35 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -166,7 +166,8 @@ arm_boot_l1pt_init:
// bits to clear in the Control Register
//
#define CPU_CONTROL_CLR \
- (CPU_CONTROL_AFLT_ENABLE_CLR)
+ (CPU_CONTROL_AFLT_ENABLE_CLR | \
+ CPU_CONTROL_TR_ENABLE)
arm_cpuinit:
// Because the MMU may already be on do a typical sequence to set
@@ -253,9 +254,7 @@ arm_cpuinit:
movt r3, #:upper16:CPU_CONTROL_SET
#endif
orr r0, r1, r3
-#if defined(CPU_CONTROL_CLR) && (CPU_CONTROL_CLR != 0)
bic r0, r0, #CPU_CONTROL_CLR
-#endif
//cmp r0, r1 // any changes to SCTLR?
//bxeq ip // no, then return.
