Module Name: src
Committed By: matt
Date: Sat Sep 16 00:47:16 UTC 2017
Modified Files:
src/sys/arch/arm/arm32: cpu.c
src/sys/arch/arm/include: armreg.h
Log Message:
Add Cortex-A35 CPU ID.
To generate a diff of this commit:
cvs rdiff -u -r1.115 -r1.116 src/sys/arch/arm/arm32/cpu.c
cvs rdiff -u -r1.111 -r1.112 src/sys/arch/arm/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/cpu.c
diff -u src/sys/arch/arm/arm32/cpu.c:1.115 src/sys/arch/arm/arm32/cpu.c:1.116
--- src/sys/arch/arm/arm32/cpu.c:1.115 Thu Jun 1 02:45:05 2017
+++ src/sys/arch/arm/arm32/cpu.c Sat Sep 16 00:47:16 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.115 2017/06/01 02:45:05 chs Exp $ */
+/* $NetBSD: cpu.c,v 1.116 2017/09/16 00:47:16 matt Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.115 2017/06/01 02:45:05 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.116 2017/09/16 00:47:16 matt Exp $");
#include <sys/systm.h>
#include <sys/conf.h>
@@ -514,6 +514,8 @@ const struct cpuidtab cpuids[] = {
pN_steppings, "7A" },
{ CPU_ID_CORTEXA17R1, CPU_CLASS_CORTEX, "Cortex-A17 r1",
pN_steppings, "7A" },
+ { CPU_ID_CORTEXA35R0, CPU_CLASS_CORTEX, "Cortex-A35 r0",
+ pN_steppings, "8A" },
{ CPU_ID_CORTEXA53R0, CPU_CLASS_CORTEX, "Cortex-A53 r0",
pN_steppings, "8A" },
{ CPU_ID_CORTEXA57R0, CPU_CLASS_CORTEX, "Cortex-A57 r0",
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.111 src/sys/arch/arm/include/armreg.h:1.112
--- src/sys/arch/arm/include/armreg.h:1.111 Tue May 17 08:27:24 2016
+++ src/sys/arch/arm/include/armreg.h Sat Sep 16 00:47:16 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.111 2016/05/17 08:27:24 msaitoh Exp $ */
+/* $NetBSD: armreg.h,v 1.112 2017/09/16 00:47:16 matt Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -227,6 +227,7 @@
#define CPU_ID_CORTEXA15R2 0x412fc0f0
#define CPU_ID_CORTEXA15R3 0x413fc0f0
#define CPU_ID_CORTEXA17R1 0x411fc0e0
+#define CPU_ID_CORTEXA35R0 0x410fd040
#define CPU_ID_CORTEXA53R0 0x410fd030
#define CPU_ID_CORTEXA57R0 0x410fd070
#define CPU_ID_CORTEXA57R1 0x411fd070
@@ -238,6 +239,7 @@
#define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080)
#define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090)
#define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0)
+#define CPU_ID_CORTEX_A35_P(n) ((n & 0xff0ff0f0) == 0x410fd040)
#define CPU_ID_CORTEX_A53_P(n) ((n & 0xff0ff0f0) == 0x410fd030)
#define CPU_ID_CORTEX_A57_P(n) ((n & 0xff0ff0f0) == 0x410fd070)
#define CPU_ID_CORTEX_A72_P(n) ((n & 0xff0ff0f0) == 0x410fd080)
