Module Name: src
Committed By: jmcneill
Date: Thu Sep 21 23:44:26 UTC 2017
Modified Files:
src/sys/arch/arm/nvidia: tegra210_car.c tegra210_carreg.h
Log Message:
Setup PLLU
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/nvidia/tegra210_car.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/nvidia/tegra210_carreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/nvidia/tegra210_car.c
diff -u src/sys/arch/arm/nvidia/tegra210_car.c:1.3 src/sys/arch/arm/nvidia/tegra210_car.c:1.4
--- src/sys/arch/arm/nvidia/tegra210_car.c:1.3 Thu Sep 21 22:54:39 2017
+++ src/sys/arch/arm/nvidia/tegra210_car.c Thu Sep 21 23:44:26 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_car.c,v 1.3 2017/09/21 22:54:39 jmcneill Exp $ */
+/* $NetBSD: tegra210_car.c,v 1.4 2017/09/21 23:44:26 jmcneill Exp $ */
/*-
* Copyright (c) 2015-2017 Jared McNeill <[email protected]>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.3 2017/09/21 22:54:39 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.4 2017/09/21 23:44:26 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -768,7 +768,26 @@ tegra210_car_xusb_init(struct tegra210_c
const bus_space_handle_t bsh = sc->sc_bsh;
uint32_t val;
- /* XXX do this all better */
+ /*
+ * Set up the PLLU (enable in software).
+ */
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_OVERRIDE, 0);
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, CAR_PLLU_MISC_IDDQ, 0);
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, 0, CAR_PLLU_MISC_IDDQ);
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT1_RSTN);
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT2_RSTN);
+ delay(5);
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_ENABLE, 0);
+ do {
+ delay(2);
+ val = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG);
+ } while ((val & CAR_PLLU_BASE_LOCK) == 0);
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_ICUSB, 0);
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_HSIC, 0);
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_USB, 0);
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RSTN, 0);
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RSTN, 0);
+ delay(2);
bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB);
Index: src/sys/arch/arm/nvidia/tegra210_carreg.h
diff -u src/sys/arch/arm/nvidia/tegra210_carreg.h:1.1 src/sys/arch/arm/nvidia/tegra210_carreg.h:1.2
--- src/sys/arch/arm/nvidia/tegra210_carreg.h:1.1 Fri Jul 21 01:01:22 2017
+++ src/sys/arch/arm/nvidia/tegra210_carreg.h Thu Sep 21 23:44:26 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_carreg.h,v 1.1 2017/07/21 01:01:22 jmcneill Exp $ */
+/* $NetBSD: tegra210_carreg.h,v 1.2 2017/09/21 23:44:26 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <[email protected]>
@@ -97,6 +97,25 @@
#define CAR_PLLU_BASE_DIVN __BITS(15,8)
#define CAR_PLLU_BASE_DIVM __BITS(4,0)
+#define CAR_PLLU_OUTA_REG 0xc4
+#define CAR_PLLU_OUTA_OUT2_RATIO __BITS(31,24)
+#define CAR_PLLU_OUTA_OUT2_OVRRIDE __BIT(18)
+#define CAR_PLLU_OUTA_OUT2_CLKEN __BIT(17)
+#define CAR_PLLU_OUTA_OUT2_RSTN __BIT(16)
+#define CAR_PLLU_OUTA_OUT1_RATIO __BITS(15,8)
+#define CAR_PLLU_OUTA_OUT1_OVRRIDE __BIT(2)
+#define CAR_PLLU_OUTA_OUT1_CLKEN __BIT(1)
+#define CAR_PLLU_OUTA_OUT1_RSTN __BIT(0)
+
+#define CAR_PLLU_MISC_REG 0xcc
+#define CAR_PLLU_MISC_IDDQ __BIT(31)
+#define CAR_PLLU_MISC_FREQLOCK __BIT(30)
+#define CAR_PLLU_MISC_EN_LCKDET __BIT(29)
+#define CAR_PLLU_MISC_PTS __BITS(28,27)
+#define CAR_PLLU_MISC_KCP __BITS(26,25)
+#define CAR_PLLU_MISC_KVCO __BIT(24)
+#define CAR_PLLU_MISC_SETUP __BITS(23,0)
+
#define CAR_PLLD_BASE_REG 0xd0
#define CAR_PLLD_BASE_BYPASS __BIT(31)
#define CAR_PLLD_BASE_ENABLE __BIT(30)
