Module Name: src
Committed By: macallan
Date: Mon Oct 30 21:41:39 UTC 2017
Modified Files:
src/sys/arch/sparc/dev: sxreg.h
Log Message:
add load & store instructions for channel data type
mostly for Xorg
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/sparc/dev/sxreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc/dev/sxreg.h
diff -u src/sys/arch/sparc/dev/sxreg.h:1.13 src/sys/arch/sparc/dev/sxreg.h:1.14
--- src/sys/arch/sparc/dev/sxreg.h:1.13 Fri Jan 13 21:49:46 2017
+++ src/sys/arch/sparc/dev/sxreg.h Mon Oct 30 21:41:39 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: sxreg.h,v 1.13 2017/01/13 21:49:46 macallan Exp $ */
+/* $NetBSD: sxreg.h,v 1.14 2017/10/30 21:41:39 macallan Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -158,6 +158,14 @@
SX_UQUAD_16 | (dreg << 7) | (o))
#define SX_LDUQ24(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \
SX_UQUAD_24 | (dreg << 7) | (o))
+#define SX_LDUC0(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \
+ SX_UCHAN_0 | (dreg << 7) | (o))
+#define SX_LDUC8(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \
+ SX_UCHAN_8 | (dreg << 7) | (o))
+#define SX_LDUC16(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \
+ SX_UCHAN_16 | (dreg << 7) | (o))
+#define SX_LDUC24(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \
+ SX_UCHAN_24 | (dreg << 7) | (o))
#define SX_ST(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \
SX_LONG | (sreg << 7) | (o))
#define SX_STM(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE_MASK | \
@@ -184,6 +192,16 @@
SX_UQUAD_16 | (sreg << 7) | (o))
#define SX_STUQ24(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \
SX_UQUAD_24 | (sreg << 7) | (o))
+#define SX_STUC0(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \
+ SX_UCHAN_0 | (sreg << 7) | (o))
+#define SX_STUC0C(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE_CLAMP | \
+ SX_UCHAN_0 | (sreg << 7) | (o))
+#define SX_STUC8(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \
+ SX_UCHAN_8 | (sreg << 7) | (o))
+#define SX_STUC16(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \
+ SX_UCHAN_16 | (sreg << 7) | (o))
+#define SX_STUC24(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \
+ SX_UCHAN_24 | (sreg << 7) | (o))
/* ROP and SELECT instructions */
#define SX_ROPB (0x0 << 21) /* mask bits apply to bytes */
