Module Name: src
Committed By: maxv
Date: Tue Oct 31 18:13:37 UTC 2017
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
Mask mxcsr, otherwise userland could set reserved bits to 1 and make
xrstor fault.
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/x86/x86/fpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/fpu.c
diff -u src/sys/arch/x86/x86/fpu.c:1.18 src/sys/arch/x86/x86/fpu.c:1.19
--- src/sys/arch/x86/x86/fpu.c:1.18 Tue Oct 31 15:16:10 2017
+++ src/sys/arch/x86/x86/fpu.c Tue Oct 31 18:13:37 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu.c,v 1.18 2017/10/31 15:16:10 maxv Exp $ */
+/* $NetBSD: fpu.c,v 1.19 2017/10/31 18:13:37 maxv Exp $ */
/*
* Copyright (c) 2008 The NetBSD Foundation, Inc. All
@@ -96,7 +96,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.18 2017/10/31 15:16:10 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.19 2017/10/31 18:13:37 maxv Exp $");
#include "opt_multiprocessor.h"
@@ -572,8 +572,12 @@ process_write_fpregs_xmm(struct lwp *l,
if (i386_use_fxsave) {
memcpy(&fpu_save->sv_xmm, fpregs, sizeof(fpu_save->sv_xmm));
- /* Invalid bits in the mxcsr_mask will cause faults */
+
+ /*
+ * Invalid bits in mxcsr or mxcsr_mask will cause faults.
+ */
fpu_save->sv_xmm.fx_mxcsr_mask &= __INITIAL_MXCSR_MASK__;
+ fpu_save->sv_xmm.fx_mxcsr &= fpu_save->sv_xmm.fx_mxcsr_mask;
/*
* Make sure the x87 and SSE bits are set in xstate_bv.
