Module Name: src
Committed By: msaitoh
Date: Mon Dec 18 04:48:28 UTC 2017
Modified Files:
src/sys/dev/pci: pci_subr.c pcireg.h ppbreg.h
Log Message:
Add VGA 16bit decode bit into the PCI bridge control register. This bit is
defined in PCI-to-PCI Bridge Architecture Specification Revision 1.2. This
bit has meaning if the VGA enable bit or the VGA Palette Snoop Enable bit is
set.
NOTE: sys/arch/x86/pci/pci_ranges.c::mmio_range_extend_by_vga_enable() and/or
some other functions should be modified.
To generate a diff of this commit:
cvs rdiff -u -r1.196 -r1.197 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.135 -r1.136 src/sys/dev/pci/pcireg.h
cvs rdiff -u -r1.7 -r1.8 src/sys/dev/pci/ppbreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.196 src/sys/dev/pci/pci_subr.c:1.197
--- src/sys/dev/pci/pci_subr.c:1.196 Wed Oct 25 08:21:41 2017
+++ src/sys/dev/pci/pci_subr.c Mon Dec 18 04:48:28 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.196 2017/10/25 08:21:41 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.197 2017/12/18 04:48:28 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.196 2017/10/25 08:21:41 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.197 2017/12/18 04:48:28 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -4290,7 +4290,7 @@ pci_conf_print_type1(
const pcireg_t *regs)
{
int off, width;
- pcireg_t rval;
+ pcireg_t rval, csreg;
uint32_t base, limit;
uint32_t base_h, limit_h;
uint64_t pbase, plimit;
@@ -4407,7 +4407,8 @@ pci_conf_print_type1(
} else
printf(" range: not set\n");
- if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
+ csreg = regs[o2i(PCI_COMMAND_STATUS_REG)];
+ if (csreg & PCI_STATUS_CAPLIST_SUPPORT)
printf(" Capability list pointer: 0x%02x\n",
PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
else
@@ -4449,6 +4450,13 @@ pci_conf_print_type1(
onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR);
onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA);
onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA);
+ /*
+ * VGA 16bit decode bit has meaning if the VGA enable bit or the
+ * VGA Palette Snoop Enable bit is set.
+ */
+ if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0)
+ || ((csreg & PCI_COMMAND_PALETTE_ENABLE) != 0))
+ onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16);
onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT);
onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR);
onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B);
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.135 src/sys/dev/pci/pcireg.h:1.136
--- src/sys/dev/pci/pcireg.h:1.135 Thu Oct 19 05:52:57 2017
+++ src/sys/dev/pci/pcireg.h Mon Dec 18 04:48:28 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.135 2017/10/19 05:52:57 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.136 2017/12/18 04:48:28 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -1327,7 +1327,7 @@ typedef u_int8_t pci_intr_line_t;
#define PCI_BRIDGE_CONTROL_SERR (1 << 1)
#define PCI_BRIDGE_CONTROL_ISA (1 << 2)
#define PCI_BRIDGE_CONTROL_VGA (1 << 3)
-/* Reserved (1 << 4) */
+#define PCI_BRIDGE_CONTROL_VGA16 (1 << 3)
#define PCI_BRIDGE_CONTROL_MABRT (1 << 5)
#define PCI_BRIDGE_CONTROL_SECBR (1 << 6)
#define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7)
Index: src/sys/dev/pci/ppbreg.h
diff -u src/sys/dev/pci/ppbreg.h:1.7 src/sys/dev/pci/ppbreg.h:1.8
--- src/sys/dev/pci/ppbreg.h:1.7 Wed May 10 03:24:31 2017
+++ src/sys/dev/pci/ppbreg.h Mon Dec 18 04:48:28 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: ppbreg.h,v 1.7 2017/05/10 03:24:31 msaitoh Exp $ */
+/* $NetBSD: ppbreg.h,v 1.8 2017/12/18 04:48:28 msaitoh Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@@ -100,6 +100,7 @@
#define PPB_BC_SERR_ENABLE (1U << (1 + PPB_BC_BITBASE))
#define PPB_BC_ISA_ENABLE (1U << (2 + PPB_BC_BITBASE))
#define PPB_BC_VGA_ENABLE (1U << (3 + PPB_BC_BITBASE))
+#define PPB_BC_VGA16_ENABLE (1U << (3 + PPB_BC_BITBASE))
#define PPB_BC_MASTER_ABORT_MODE (1U << (5 + PPB_BC_BITBASE))
#define PPB_BC_SECONDARY_RESET (1U << (6 + PPB_BC_BITBASE))
#define PPB_BC_FAST_B2B_ENABLE (1U << (7 + PPB_BC_BITBASE))
