Module Name: src
Committed By: macallan
Date: Fri Feb 16 18:04:06 UTC 2018
Modified Files:
src/sys/arch/powerpc/include/oea: hid.h spr.h
Log Message:
add a few pp970-specific bits
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/powerpc/include/oea/hid.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/powerpc/include/oea/spr.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/powerpc/include/oea/hid.h
diff -u src/sys/arch/powerpc/include/oea/hid.h:1.11 src/sys/arch/powerpc/include/oea/hid.h:1.12
--- src/sys/arch/powerpc/include/oea/hid.h:1.11 Fri Jul 7 22:13:35 2017
+++ src/sys/arch/powerpc/include/oea/hid.h Fri Feb 16 18:04:06 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: hid.h,v 1.11 2017/07/07 22:13:35 macallan Exp $ */
+/* $NetBSD: hid.h,v 1.12 2018/02/16 18:04:06 macallan Exp $ */
/*-
* Copyright (c) 2000 Tsubai Masanari. All rights reserved.
@@ -172,4 +172,18 @@
#define HID1_SYNCBE 0x00000800 /* Enable sync/eieio broadcast */
#define HID1_ABE 0x00000400 /* Enable address broadcast */
+/* PPC970 HID4 */
+#define HID4_RMLR0 0x0000000000000020 /* real mode limit bit 0 */
+#define HID4_RMLR1 0x4000000000000000 /* real mode limit bit 1 */
+#define HID4_RMLR2 0x2000000000000000 /* real mode limit bit 2 */
+/*
+ * real mode limit bits 012
+ * 011 - 64MB
+ * 111 - 128MB
+ * 100 - 256MB
+ * x10 - 1GB
+ * x01 - 16GB
+ * 000 - 256GB
+ */
+
#endif /* _POWERPC_OEA_HID_H_ */
Index: src/sys/arch/powerpc/include/oea/spr.h
diff -u src/sys/arch/powerpc/include/oea/spr.h:1.3 src/sys/arch/powerpc/include/oea/spr.h:1.4
--- src/sys/arch/powerpc/include/oea/spr.h:1.3 Tue Jul 7 15:41:46 2015
+++ src/sys/arch/powerpc/include/oea/spr.h Fri Feb 16 18:04:06 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: spr.h,v 1.3 2015/07/07 15:41:46 macallan Exp $ */
+/* $NetBSD: spr.h,v 1.4 2018/02/16 18:04:06 macallan Exp $ */
#ifndef _POWERPC_OEA_SPR_H_
#define _POWERPC_OEA_SPR_H_
@@ -28,6 +28,15 @@
#define SPR_RTCL_W 0x015 /* ..6. 601 RTC Lower - Write */
#define SPR_SDR1 0x019 /* ..68 Page table base address register */
#define SPR_VRSAVE 0x100 /* ..6. AltiVec VRSAVE */
+#define SPR_SCOMC 0x114 /* .... SCOM Control Register (970) */
+#define SPR_SCOMD 0x115 /* .... SCOM Data Register (970) */
+#define SCOM_PCR 0x0aa00100 /* Power Control Register */
+#define SCOM_PCR_BIT 0x80000000 /* Data bit */
+#define SCOM_PSR 0x40800100 /* Power Status Register */
+#define PSR_RECEIVED (1ULL << 61)
+#define PSR_COMPLETED (1ULL << 60)
+#define SCOMC_READ 0x00008000
+#define SCOMC_WRITE 0x00000000
#define SPR_ASR 0x118 /* ..6. Address Space Register (PPC64) */
#define SPR_EAR 0x11a /* ..68 External Access Register */
#define MPC601 0x0001
