Module Name: src
Committed By: knakahara
Date: Tue Feb 20 08:49:23 UTC 2018
Modified Files:
src/sys/dev/pci/ixgbe: ixgbe.c
Log Message:
Improve a comment about reading EICS register defined write-only by spec.
It seems that is workaround for silicon errata.
ok by [email protected].
To generate a diff of this commit:
cvs rdiff -u -r1.124 -r1.125 src/sys/dev/pci/ixgbe/ixgbe.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/ixgbe/ixgbe.c
diff -u src/sys/dev/pci/ixgbe/ixgbe.c:1.124 src/sys/dev/pci/ixgbe/ixgbe.c:1.125
--- src/sys/dev/pci/ixgbe/ixgbe.c:1.124 Tue Feb 20 07:24:37 2018
+++ src/sys/dev/pci/ixgbe/ixgbe.c Tue Feb 20 08:49:23 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe.c,v 1.124 2018/02/20 07:24:37 msaitoh Exp $ */
+/* $NetBSD: ixgbe.c,v 1.125 2018/02/20 08:49:23 knakahara Exp $ */
/******************************************************************************
@@ -2838,6 +2838,12 @@ ixgbe_msix_link(void *arg)
IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_OTHER);
/* First get the cause */
+ /*
+ * The specifications of 82598, 82599, X540 and X550 say EICS register
+ * is write only. However, Linux says it is a workaround for silicon
+ * errata to read EICS instead of EICR to get interrupt cause. It seems
+ * there is a problem about read clear mechanism for EICR register.
+ */
eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
/* Be sure the queue bits are not cleared */
eicr &= ~IXGBE_EICR_RTX_QUEUE;
