Module Name: src
Committed By: martin
Date: Wed Mar 7 14:50:57 UTC 2018
Modified Files:
src/sys/arch/amd64/amd64 [netbsd-8]: amd64_trap.S locore.S trap.c
vector.S
src/sys/arch/amd64/conf [netbsd-8]: files.amd64
src/sys/arch/amd64/include [netbsd-8]: frameasm.h
src/sys/arch/x86/x86 [netbsd-8]: cpu.c
src/sys/arch/xen/conf [netbsd-8]: Makefile.xen
Log Message:
Pull up the following revisions (via patch), requested by maxv in ticket #610:
sys/arch/amd64/amd64/amd64_trap.S 1.8,1.10,1.12 (partial),1.13-1.15,
1.19 (partial),1.20,1.21,1.22,1.24
(via patch)
sys/arch/amd64/amd64/locore.S 1.129 (partial),1.132 (via patch)
sys/arch/amd64/amd64/trap.c 1.97 (partial),1.111 (via patch)
sys/arch/amd64/amd64/vector.S 1.54,1.55 (via patch)
sys/arch/amd64/include/frameasm.h 1.21,1.23 (via patch)
sys/arch/x86/x86/cpu.c 1.138 (via patch)
sys/arch/xen/conf/Makefile.xen 1.45 (via patch)
Rename and reorder several things in amd64_trap.S.
Compile amd64_trap.S as a file.
Introduce nmitrap and doubletrap.
Have the CPU clear PSL_D automatically in the syscall entry point.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.5.6.1 src/sys/arch/amd64/amd64/amd64_trap.S
cvs rdiff -u -r1.123.6.2 -r1.123.6.3 src/sys/arch/amd64/amd64/locore.S
cvs rdiff -u -r1.96 -r1.96.4.1 src/sys/arch/amd64/amd64/trap.c
cvs rdiff -u -r1.49 -r1.49.2.1 src/sys/arch/amd64/amd64/vector.S
cvs rdiff -u -r1.88.8.1 -r1.88.8.2 src/sys/arch/amd64/conf/files.amd64
cvs rdiff -u -r1.20 -r1.20.32.1 src/sys/arch/amd64/include/frameasm.h
cvs rdiff -u -r1.130.2.1 -r1.130.2.2 src/sys/arch/x86/x86/cpu.c
cvs rdiff -u -r1.41 -r1.41.6.1 src/sys/arch/xen/conf/Makefile.xen
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/amd64/amd64/amd64_trap.S
diff -u src/sys/arch/amd64/amd64/amd64_trap.S:1.5 src/sys/arch/amd64/amd64/amd64_trap.S:1.5.6.1
--- src/sys/arch/amd64/amd64/amd64_trap.S:1.5 Fri Mar 24 18:03:32 2017
+++ src/sys/arch/amd64/amd64/amd64_trap.S Wed Mar 7 14:50:56 2018
@@ -1,11 +1,11 @@
-/* $NetBSD: amd64_trap.S,v 1.5 2017/03/24 18:03:32 maxv Exp $ */
+/* $NetBSD: amd64_trap.S,v 1.5.6.1 2018/03/07 14:50:56 martin Exp $ */
-/*-
- * Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
+/*
+ * Copyright (c) 1998, 2007, 2008, 2017 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
- * by Charles M. Hannum and by Andrew Doran.
+ * by Charles M. Hannum, by Andrew Doran and by Maxime Villard.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -64,10 +64,19 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#if 0
#include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: amd64_trap.S,v 1.5 2017/03/24 18:03:32 maxv Exp $");
-#endif
+
+#include "opt_xen.h"
+#include "opt_dtrace.h"
+
+#define ALIGN_TEXT .align 16,0x90
+
+#include <machine/frameasm.h>
+#include <machine/segments.h>
+#include <machine/trap.h>
+#include <machine/specialreg.h>
+
+#include "assym.h"
/*
* Trap and fault vector routines
@@ -78,12 +87,10 @@ __KERNEL_RCSID(0, "$NetBSD: amd64_trap.S
* (possibly the next clock tick). Thus, we disable interrupt before checking,
* and only enable them again on the final `iret' or before calling the AST
* handler.
- */
-
-/*****************************************************************************/
+ */
#ifdef XEN
-#define PRE_TRAP movq (%rsp),%rcx ; movq 8(%rsp),%r11 ; addq $0x10,%rsp
+#define PRE_TRAP movq (%rsp),%rcx ; movq 8(%rsp),%r11 ; addq $0x10,%rsp
#else
#define PRE_TRAP
#endif
@@ -118,10 +125,10 @@ IDTVEC(trap02)
#if defined(XEN)
ZTRAP(T_NMI)
#else
- pushq $0
- pushq $T_NMI
+ ZTRAP_NJ(T_NMI)
subq $TF_REGSIZE,%rsp
INTR_SAVE_GPRS
+ cld
movw %gs,TF_GS(%rsp)
movw %fs,TF_FS(%rsp)
movw %es,TF_ES(%rsp)
@@ -130,23 +137,21 @@ IDTVEC(trap02)
movl $MSR_GSBASE,%ecx
rdmsr
cmpl $VM_MIN_KERNEL_ADDRESS_HIGH32,%edx
- jae noswapgs
+ jae .Lnoswapgs
swapgs
movq %rsp,%rdi
incq CPUVAR(NTRAP)
- call _C_LABEL(trap)
+ call _C_LABEL(nmitrap)
swapgs
- jmp nmileave
+ jmp .Lnmileave
-noswapgs:
+.Lnoswapgs:
movq %rsp,%rdi
incq CPUVAR(NTRAP)
- call _C_LABEL(trap)
+ call _C_LABEL(nmitrap)
-nmileave:
- movw TF_ES(%rsp),%es
- movw TF_DS(%rsp),%ds
+.Lnmileave:
INTR_RESTORE_GPRS
addq $TF_REGSIZE+16,%rsp
iretq
@@ -179,21 +184,6 @@ IDTVEC(trap03)
/* Jump to the code hooked in by DTrace. */
movq dtrace_invop_jump_addr, %rax
jmpq *dtrace_invop_jump_addr
-
- .bss
- .globl dtrace_invop_jump_addr
- .align 8
- .type dtrace_invop_jump_addr, @object
- .size dtrace_invop_jump_addr, 8
-dtrace_invop_jump_addr:
- .zero 8
- .globl dtrace_invop_calltrap_addr
- .align 8
- .type dtrace_invop_calltrap_addr, @object
- .size dtrace_invop_calltrap_addr, 8
-dtrace_invop_calltrap_addr:
- .zero 8
- .text
#endif
IDTVEC_END(trap03)
@@ -214,23 +204,55 @@ IDTVEC(trap07)
INTRENTRY
#ifdef DIAGNOSTIC
movl CPUVAR(ILEVEL),%ebx
-#endif /* DIAGNOSTIC */
+#endif
movq %rsp,%rdi
call _C_LABEL(fpudna)
jmp .Lalltraps_checkusr
IDTVEC_END(trap07)
+/*
+ * Double faults execute on a particular stack, and we must not jump out
+ * of it. So don't enable interrupts.
+ */
IDTVEC(trap08)
+#if defined(XEN)
TRAP(T_DOUBLEFLT)
+#else
+ TRAP_NJ(T_DOUBLEFLT)
+ subq $TF_REGSIZE,%rsp
+ INTR_SAVE_GPRS
+ testb $SEL_UPL,TF_CS(%rsp)
+ jz 1f
+ swapgs
+1:
+ cld
+ movw %gs,TF_GS(%rsp)
+ movw %fs,TF_FS(%rsp)
+ movw %es,TF_ES(%rsp)
+ movw %ds,TF_DS(%rsp)
+
+ movq %rsp,%rdi
+ incq CPUVAR(NTRAP)
+ call _C_LABEL(doubletrap)
+
+ INTR_RESTORE_GPRS
+
+ testb $SEL_UPL,TF_CS(%rsp)
+ jz 1f
+ swapgs
+1:
+ addq $TF_REGSIZE+16,%rsp
+ iretq
+#endif
IDTVEC_END(trap08)
IDTVEC(trap09)
ZTRAP(T_FPOPFLT)
IDTVEC_END(trap09)
-IDTVEC(trap0a)
+IDTVEC(trap10)
TRAP(T_TSSFLT)
-IDTVEC_END(trap0a)
+IDTVEC_END(trap10)
#ifdef XEN
/*
@@ -241,148 +263,101 @@ IDTVEC_END(trap0a)
#define check_swapgs alltraps
#endif
-IDTVEC(trap0b) /* #NP() Segment not present */
+IDTVEC(trap11) /* #NP() Segment not present */
TRAP_NJ(T_SEGNPFLT)
jmp check_swapgs
-IDTVEC_END(trap0b)
+IDTVEC_END(trap11)
-IDTVEC(trap0c) /* #SS() Stack exception */
+IDTVEC(trap12) /* #SS() Stack exception */
TRAP_NJ(T_STKFLT)
jmp check_swapgs
-IDTVEC_END(trap0c)
+IDTVEC_END(trap12)
-IDTVEC(trap0d) /* #GP() General protection */
+IDTVEC(trap13) /* #GP() General protection */
TRAP_NJ(T_PROTFLT)
-#ifdef check_swapgs
jmp check_swapgs
-#else
-/*
- * We need to worry about traps in kernel mode while the kernel %gs isn't
- * loaded. These are either faults on iretq during return to user or loads to
- * %gs.
- *
- * When such traps happen, we have CPL=0 and %gs=userland, and we must perform
- * an additional swapgs to get %gs=kernel.
- */
-check_swapgs:
- INTRENTRY_L(3f,1:)
-2:
- sti
- jmp calltrap
-3:
- /*
- * Trap in kernel mode.
- */
- /* Case 1: fault on iretq? */
- movq TF_RIP(%rsp),%rax
- cmpw $0xcf48,(%rax) /* Faulting instruction is iretq ? */
- jne 5f /* Jump if not */
- movq TF_RSP(%rsp),%rax /* Must read %rsp, may be a pad word */
- testb $SEL_UPL,8(%rax) /* Check %cs of outer iret frame */
- je 2b /* jump if iret was to kernel */
- jmp 1b /* to user - must restore %gs */
-5:
-
- /* Case 2: move to %gs? */
- movw (%rax),%ax
- andb $070,%ah /* mask mod/rm from mod/reg/rm */
- cmpw $0x8e+050*256,%ax /* Any move to %gs (reg 5) */
- jne 2b /* No - normal kernel fault */
- jmp 1b /* Yes - restore %gs */
-#endif
-IDTVEC_END(trap0d)
+IDTVEC_END(trap13)
-IDTVEC(trap0e)
+IDTVEC(trap14)
TRAP(T_PAGEFLT)
-IDTVEC_END(trap0e)
+IDTVEC_END(trap14)
-IDTVEC(intrspurious)
-IDTVEC(trap0f)
+IDTVEC(trap15)
ZTRAP_NJ(T_ASTFLT)
INTRENTRY
#ifdef DIAGNOSTIC
movl CPUVAR(ILEVEL),%ebx
-#endif /* DIAGNOSTIC */
+#endif
jmp .Lalltraps_checkusr
-IDTVEC_END(trap0f)
-IDTVEC_END(intrspurious)
+IDTVEC_END(trap15)
-IDTVEC(trap10)
+IDTVEC(trap16)
ZTRAP_NJ(T_ARITHTRAP)
.Ldo_fputrap:
INTRENTRY
#ifdef DIAGNOSTIC
movl CPUVAR(ILEVEL),%ebx
-#endif /* DIAGNOSTIC */
+#endif
movq %rsp,%rdi
call _C_LABEL(fputrap)
jmp .Lalltraps_checkusr
-IDTVEC_END(trap10)
+IDTVEC_END(trap16)
-IDTVEC(trap11)
+IDTVEC(trap17)
TRAP(T_ALIGNFLT)
-IDTVEC_END(trap11)
+IDTVEC_END(trap17)
-IDTVEC(trap12)
+IDTVEC(trap18)
ZTRAP(T_MCA)
-IDTVEC_END(trap12)
+IDTVEC_END(trap18)
-IDTVEC(trap13)
+IDTVEC(trap19)
ZTRAP_NJ(T_XMM)
jmp .Ldo_fputrap
-IDTVEC_END(trap13)
+IDTVEC_END(trap19)
-IDTVEC(trap14)
-IDTVEC(trap15)
-IDTVEC(trap16)
-IDTVEC(trap17)
-IDTVEC(trap18)
-IDTVEC(trap19)
-IDTVEC(trap1a)
-IDTVEC(trap1b)
-IDTVEC(trap1c)
-IDTVEC(trap1d)
-IDTVEC(trap1e)
-IDTVEC(trap1f)
+IDTVEC(trap20)
+IDTVEC(trap21)
+IDTVEC(trap22)
+IDTVEC(trap23)
+IDTVEC(trap24)
+IDTVEC(trap25)
+IDTVEC(trap26)
+IDTVEC(trap27)
+IDTVEC(trap28)
+IDTVEC(trap29)
+IDTVEC(trap30)
+IDTVEC(trap31)
/* 20 - 31 reserved for future exp */
ZTRAP(T_RESERVED)
-IDTVEC_END(trap1f)
-IDTVEC_END(trap1e)
-IDTVEC_END(trap1d)
-IDTVEC_END(trap1c)
-IDTVEC_END(trap1b)
-IDTVEC_END(trap1a)
-IDTVEC_END(trap19)
-IDTVEC_END(trap18)
-IDTVEC_END(trap17)
-IDTVEC_END(trap16)
-IDTVEC_END(trap15)
-IDTVEC_END(trap14)
+IDTVEC_END(trap20)
+IDTVEC_END(trap21)
+IDTVEC_END(trap22)
+IDTVEC_END(trap23)
+IDTVEC_END(trap24)
+IDTVEC_END(trap25)
+IDTVEC_END(trap26)
+IDTVEC_END(trap27)
+IDTVEC_END(trap28)
+IDTVEC_END(trap29)
+IDTVEC_END(trap30)
+IDTVEC_END(trap31)
+
+IDTVEC(intrspurious)
+ ZTRAP_NJ(T_ASTFLT)
+ INTRENTRY
+#ifdef DIAGNOSTIC
+ movl CPUVAR(ILEVEL),%ebx
+#endif
+ jmp .Lalltraps_checkusr
+IDTVEC_END(intrspurious)
-IDTVEC(exceptions)
- .quad _C_LABEL(Xtrap00), _C_LABEL(Xtrap01)
- .quad _C_LABEL(Xtrap02), _C_LABEL(Xtrap03)
- .quad _C_LABEL(Xtrap04), _C_LABEL(Xtrap05)
- .quad _C_LABEL(Xtrap06), _C_LABEL(Xtrap07)
- .quad _C_LABEL(Xtrap08), _C_LABEL(Xtrap09)
- .quad _C_LABEL(Xtrap0a), _C_LABEL(Xtrap0b)
- .quad _C_LABEL(Xtrap0c), _C_LABEL(Xtrap0d)
- .quad _C_LABEL(Xtrap0e), _C_LABEL(Xtrap0f)
- .quad _C_LABEL(Xtrap10), _C_LABEL(Xtrap11)
- .quad _C_LABEL(Xtrap12), _C_LABEL(Xtrap13)
- .quad _C_LABEL(Xtrap14), _C_LABEL(Xtrap15)
- .quad _C_LABEL(Xtrap16), _C_LABEL(Xtrap17)
- .quad _C_LABEL(Xtrap18), _C_LABEL(Xtrap19)
- .quad _C_LABEL(Xtrap1a), _C_LABEL(Xtrap1b)
- .quad _C_LABEL(Xtrap1c), _C_LABEL(Xtrap1d)
- .quad _C_LABEL(Xtrap1e), _C_LABEL(Xtrap1f)
-IDTVEC_END(exceptions)
/*
* trap() calls here when it detects a fault in INTRFASTEXIT (loading the
- * segment registers or during the iret itself).
- * The address of the (possibly reconstructed) user trap frame is
- * passed as an argument.
+ * segment registers or during the iret itself). The address of the (possibly
+ * reconstructed) user trap frame is passed as an argument.
+ *
* Typically the code will have raised a SIGSEGV which will be actioned
* by the code below.
*/
@@ -392,10 +367,47 @@ LABEL(trap_return_fault_return)
#ifdef DIAGNOSTIC
/* We can't recover the saved %rbx, so suppress warning */
movl CPUVAR(ILEVEL),%ebx
-#endif /* DIAGNOSTIC */
+#endif
jmp .Lalltraps_checkusr
END(trap_return_fault_return)
+#ifndef check_swapgs
+/*
+ * We need to worry about traps in kernel mode while the kernel %gs isn't
+ * loaded. These are either faults on iretq during return to user or loads to
+ * %gs.
+ *
+ * When such traps happen, we have CPL=0 and %gs=userland, and we must perform
+ * an additional swapgs to get %gs=kernel.
+ */
+NENTRY(check_swapgs)
+ INTRENTRY_L(3f,1:)
+2:
+ sti
+ jmp calltrap
+3:
+ /*
+ * Trap in kernel mode.
+ */
+ /* Case 1: fault on iretq? */
+ movq TF_RIP(%rsp),%rax
+ cmpw $0xcf48,(%rax) /* Faulting instruction is iretq ? */
+ jne 5f /* Jump if not */
+ movq TF_RSP(%rsp),%rax /* Must read %rsp, may be a pad word */
+ testb $SEL_UPL,8(%rax) /* Check %cs of outer iret frame */
+ je 2b /* jump if iret was to kernel */
+ jmp 1b /* to user - must restore %gs */
+5:
+
+ /* Case 2: move to %gs? */
+ movw (%rax),%ax
+ andb $070,%ah /* mask mod/rm from mod/reg/rm */
+ cmpw $0x8e+050*256,%ax /* Any move to %gs (reg 5) */
+ jne 2b /* No - normal kernel fault */
+ jmp 1b /* Yes - restore %gs */
+END(check_swapgs)
+#endif
+
/*
* All traps go through here. Call the generic trap handler, and
* check for ASTs afterwards.
@@ -407,13 +419,15 @@ NENTRY(alltraps)
calltrap:
#ifdef DIAGNOSTIC
movl CPUVAR(ILEVEL),%ebx
-#endif /* DIAGNOSTIC */
+#endif
movq %rsp,%rdi
incq CPUVAR(NTRAP)
call _C_LABEL(trap)
+
.Lalltraps_checkusr:
testb $SEL_RPL,TF_CS(%rsp)
jz 6f
+
.Lalltraps_checkast:
movq CPUVAR(CURLWP),%r14
/* Check for ASTs on exit to user mode. */
@@ -429,13 +443,21 @@ calltrap:
jmp .Lalltraps_checkast /* re-check ASTs */
3: CHECK_DEFERRED_SWITCH
jnz 9f
-#ifndef DIAGNOSTIC
-6: INTRFASTEXIT
-#else /* DIAGNOSTIC */
-6: cmpl CPUVAR(ILEVEL),%ebx
- jne 3f
+
+6:
+#ifdef DIAGNOSTIC
+ cmpl CPUVAR(ILEVEL),%ebx
+ jne .Lspl_error
+#endif
INTRFASTEXIT
-3: STI(si)
+
+9: STI(si)
+ call _C_LABEL(do_pmap_load)
+ jmp .Lalltraps_checkast /* re-check ASTs */
+
+#ifdef DIAGNOSTIC
+.Lspl_error:
+ STI(si)
movabsq $4f,%rdi
movl CPUVAR(ILEVEL),%esi
movl %ebx,%edx
@@ -445,8 +467,43 @@ calltrap:
call _C_LABEL(spllower)
jmp .Lalltraps_checkast
4: .asciz "WARNING: SPL NOT LOWERED ON TRAP EXIT %x %x\n"
-#endif /* DIAGNOSTIC */
-9: STI(si)
- call _C_LABEL(do_pmap_load)
- jmp .Lalltraps_checkast /* re-check ASTs */
+#endif
END(alltraps)
+
+#ifdef KDTRACE_HOOKS
+ .bss
+ .globl dtrace_invop_jump_addr
+ .align 8
+ .type dtrace_invop_jump_addr, @object
+ .size dtrace_invop_jump_addr, 8
+dtrace_invop_jump_addr:
+ .zero 8
+ .globl dtrace_invop_calltrap_addr
+ .align 8
+ .type dtrace_invop_calltrap_addr, @object
+ .size dtrace_invop_calltrap_addr, 8
+dtrace_invop_calltrap_addr:
+ .zero 8
+#endif
+
+ .section .rodata
+
+IDTVEC(exceptions)
+ .quad _C_LABEL(Xtrap00), _C_LABEL(Xtrap01)
+ .quad _C_LABEL(Xtrap02), _C_LABEL(Xtrap03)
+ .quad _C_LABEL(Xtrap04), _C_LABEL(Xtrap05)
+ .quad _C_LABEL(Xtrap06), _C_LABEL(Xtrap07)
+ .quad _C_LABEL(Xtrap08), _C_LABEL(Xtrap09)
+ .quad _C_LABEL(Xtrap10), _C_LABEL(Xtrap11)
+ .quad _C_LABEL(Xtrap12), _C_LABEL(Xtrap13)
+ .quad _C_LABEL(Xtrap14), _C_LABEL(Xtrap15)
+ .quad _C_LABEL(Xtrap16), _C_LABEL(Xtrap17)
+ .quad _C_LABEL(Xtrap18), _C_LABEL(Xtrap19)
+ .quad _C_LABEL(Xtrap20), _C_LABEL(Xtrap21)
+ .quad _C_LABEL(Xtrap22), _C_LABEL(Xtrap23)
+ .quad _C_LABEL(Xtrap24), _C_LABEL(Xtrap25)
+ .quad _C_LABEL(Xtrap26), _C_LABEL(Xtrap27)
+ .quad _C_LABEL(Xtrap28), _C_LABEL(Xtrap29)
+ .quad _C_LABEL(Xtrap30), _C_LABEL(Xtrap31)
+IDTVEC_END(exceptions)
+
Index: src/sys/arch/amd64/amd64/locore.S
diff -u src/sys/arch/amd64/amd64/locore.S:1.123.6.2 src/sys/arch/amd64/amd64/locore.S:1.123.6.3
--- src/sys/arch/amd64/amd64/locore.S:1.123.6.2 Mon Sep 4 20:41:28 2017
+++ src/sys/arch/amd64/amd64/locore.S Wed Mar 7 14:50:56 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.123.6.2 2017/09/04 20:41:28 snj Exp $ */
+/* $NetBSD: locore.S,v 1.123.6.3 2018/03/07 14:50:56 martin Exp $ */
/*
* Copyright-o-rama!
@@ -1282,6 +1282,7 @@ IDTVEC(syscall)
pushq $T_ASTFLT
subq $TF_REGSIZE,%rsp
INTR_SAVE_GPRS
+ cld
movw %fs,TF_FS(%rsp)
movw %gs,TF_GS(%rsp)
movw %es,TF_ES(%rsp)
@@ -1468,3 +1469,16 @@ ENTRY(pagezero)
sfence
ret
END(pagezero)
+
+ _ALIGN_TEXT
+LABEL(intrfastexit)
+ INTR_RESTORE_GPRS
+ testq $SEL_UPL,TF_CS(%rsp)
+ je 99f
+ NOT_XEN(cli;)
+ movw TF_ES(%rsp),%es
+ movw TF_DS(%rsp),%ds
+ SWAPGS
+99: addq $TF_REGSIZE+16,%rsp
+ iretq
+END(intrfastexit)
Index: src/sys/arch/amd64/amd64/trap.c
diff -u src/sys/arch/amd64/amd64/trap.c:1.96 src/sys/arch/amd64/amd64/trap.c:1.96.4.1
--- src/sys/arch/amd64/amd64/trap.c:1.96 Mon Apr 24 17:03:43 2017
+++ src/sys/arch/amd64/amd64/trap.c Wed Mar 7 14:50:56 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.96 2017/04/24 17:03:43 chs Exp $ */
+/* $NetBSD: trap.c,v 1.96.4.1 2018/03/07 14:50:56 martin Exp $ */
/*-
* Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
@@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.96 2017/04/24 17:03:43 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.96.4.1 2018/03/07 14:50:56 martin Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -126,6 +126,8 @@ dtrace_trap_func_t dtrace_trap_func = NU
dtrace_doubletrap_func_t dtrace_doubletrap_func = NULL;
#endif
+void nmitrap(struct trapframe *);
+void doubletrap(struct trapframe *);
void trap(struct trapframe *);
void trap_return_fault_return(struct trapframe *) __dead;
@@ -210,6 +212,39 @@ trap_print(const struct trapframe *frame
l, l->l_proc->p_pid, l->l_lid, KSTACK_LOWEST_ADDR(l));
}
+void
+nmitrap(struct trapframe *frame)
+{
+ const int type = T_NMI;
+
+ if (nmi_dispatch(frame))
+ return;
+ /* NMI can be hooked up to a pushbutton for debugging */
+ if (kgdb_trap(type, frame))
+ return;
+ if (kdb_trap(type, 0, frame))
+ return;
+ /* machine/parity/power fail/"kitchen sink" faults */
+
+ x86_nmi();
+}
+
+void
+doubletrap(struct trapframe *frame)
+{
+ const int type = T_DOUBLEFLT;
+ struct lwp *l = curlwp;
+
+ trap_print(frame, l);
+
+ if (kdb_trap(type, 0, frame))
+ return;
+ if (kgdb_trap(type, frame))
+ return;
+
+ panic("double fault");
+}
+
/*
* trap(frame): exception, fault, and trap interface to BSD kernel.
*
@@ -257,7 +292,7 @@ trap(struct trapframe *frame)
trap_print(frame, l);
}
#endif
- if (type != T_NMI && !KERNELMODE(frame->tf_cs, frame->tf_rflags)) {
+ if (!KERNELMODE(frame->tf_cs, frame->tf_rflags)) {
type |= T_USER;
l->l_md.md_regs = frame;
LWP_CACHE_CREDS(l, p);
@@ -747,19 +782,6 @@ faultcommon:
(*p->p_emul->e_trapsignal)(l, &ksi);
}
break;
-
- case T_NMI:
- if (nmi_dispatch(frame))
- return;
- /* NMI can be hooked up to a pushbutton for debugging */
- if (kgdb_trap(type, frame))
- return;
- if (kdb_trap(type, 0, frame))
- return;
- /* machine/parity/power fail/"kitchen sink" faults */
-
- x86_nmi();
- return;
}
if ((type & T_USER) == 0)
Index: src/sys/arch/amd64/amd64/vector.S
diff -u src/sys/arch/amd64/amd64/vector.S:1.49 src/sys/arch/amd64/amd64/vector.S:1.49.2.1
--- src/sys/arch/amd64/amd64/vector.S:1.49 Tue May 23 08:54:38 2017
+++ src/sys/arch/amd64/amd64/vector.S Wed Mar 7 14:50:56 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: vector.S,v 1.49 2017/05/23 08:54:38 nonaka Exp $ */
+/* $NetBSD: vector.S,v 1.49.2.1 2018/03/07 14:50:56 martin Exp $ */
/*-
* Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
@@ -85,11 +85,7 @@
#include "lapic.h"
#include "assym.h"
-#include "amd64_trap.S"
-
-/*****************************************************************************/
-
-#define __HAVE_GENERIC_SOFT_INTERRUPTS /* XXX */
+ .text
/*
* Macros for interrupt entry, call to handler, and exit.
Index: src/sys/arch/amd64/conf/files.amd64
diff -u src/sys/arch/amd64/conf/files.amd64:1.88.8.1 src/sys/arch/amd64/conf/files.amd64:1.88.8.2
--- src/sys/arch/amd64/conf/files.amd64:1.88.8.1 Tue Aug 1 23:18:30 2017
+++ src/sys/arch/amd64/conf/files.amd64 Wed Mar 7 14:50:57 2018
@@ -1,4 +1,4 @@
-# $NetBSD: files.amd64,v 1.88.8.1 2017/08/01 23:18:30 snj Exp $
+# $NetBSD: files.amd64,v 1.88.8.2 2018/03/07 14:50:57 martin Exp $
#
# new style config file for amd64 architecture
#
@@ -35,6 +35,7 @@ file arch/amd64/amd64/copy.S machdep
file arch/amd64/amd64/spl.S machdep
file arch/amd64/amd64/amd64func.S machdep
+file arch/amd64/amd64/amd64_trap.S machdep
file arch/amd64/amd64/autoconf.c machdep
file arch/amd64/amd64/busfunc.S machdep
file arch/amd64/amd64/cpu_in_cksum.S (inet | inet6) & cpu_in_cksum
Index: src/sys/arch/amd64/include/frameasm.h
diff -u src/sys/arch/amd64/include/frameasm.h:1.20 src/sys/arch/amd64/include/frameasm.h:1.20.32.1
--- src/sys/arch/amd64/include/frameasm.h:1.20 Sun Jul 15 15:17:56 2012
+++ src/sys/arch/amd64/include/frameasm.h Wed Mar 7 14:50:57 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: frameasm.h,v 1.20 2012/07/15 15:17:56 dsl Exp $ */
+/* $NetBSD: frameasm.h,v 1.20.32.1 2018/03/07 14:50:57 martin Exp $ */
#ifndef _AMD64_MACHINE_FRAMEASM_H
#define _AMD64_MACHINE_FRAMEASM_H
@@ -55,8 +55,7 @@
movq %r15,TF_R15(%rsp) ; \
movq %rbp,TF_RBP(%rsp) ; \
movq %rbx,TF_RBX(%rsp) ; \
- movq %rax,TF_RAX(%rsp) ; \
- cld
+ movq %rax,TF_RAX(%rsp)
#define INTR_RESTORE_GPRS \
movq TF_RDI(%rsp),%rdi ; \
@@ -78,6 +77,7 @@
#define INTRENTRY_L(kernel_trap, usertrap) \
subq $TF_REGSIZE,%rsp ; \
INTR_SAVE_GPRS ; \
+ cld ; \
testb $SEL_UPL,TF_CS(%rsp) ; \
je kernel_trap ; \
usertrap ; \
@@ -92,16 +92,7 @@ usertrap ; \
98:
#define INTRFASTEXIT \
- INTR_RESTORE_GPRS ; \
- testq $SEL_UPL,TF_CS(%rsp) /* Interrupted %cs */ ; \
- je 99f ; \
-/* Disable interrupts until the 'iret', user registers loaded. */ \
- NOT_XEN(cli;) \
- movw TF_ES(%rsp),%es ; \
- movw TF_DS(%rsp),%ds ; \
- SWAPGS ; \
-99: addq $TF_REGSIZE+16,%rsp /* + T_xxx and error code */ ; \
- iretq
+ jmp intrfastexit
#define INTR_RECURSE_HWFRAME \
movq %rsp,%r10 ; \
@@ -115,12 +106,6 @@ usertrap ; \
XEN_ONLY2(andb $0xfc,(%rsp);) \
pushq %r13 ;
-#define DO_DEFERRED_SWITCH \
- cmpl $0, CPUVAR(WANT_PMAPLOAD) ; \
- jz 1f ; \
- call _C_LABEL(do_pmap_load) ; \
-1:
-
#define CHECK_DEFERRED_SWITCH \
cmpl $0, CPUVAR(WANT_PMAPLOAD)
Index: src/sys/arch/x86/x86/cpu.c
diff -u src/sys/arch/x86/x86/cpu.c:1.130.2.1 src/sys/arch/x86/x86/cpu.c:1.130.2.2
--- src/sys/arch/x86/x86/cpu.c:1.130.2.1 Wed Jun 14 04:47:33 2017
+++ src/sys/arch/x86/x86/cpu.c Wed Mar 7 14:50:57 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.130.2.1 2017/06/14 04:47:33 snj Exp $ */
+/* $NetBSD: cpu.c,v 1.130.2.2 2018/03/07 14:50:57 martin Exp $ */
/*-
* Copyright (c) 2000-2012 NetBSD Foundation, Inc.
@@ -62,7 +62,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.130.2.1 2017/06/14 04:47:33 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.130.2.2 2018/03/07 14:50:57 martin Exp $");
#include "opt_ddb.h"
#include "opt_mpbios.h" /* for MPDEBUG */
@@ -1125,7 +1125,7 @@ cpu_init_msrs(struct cpu_info *ci, bool
((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48));
wrmsr(MSR_LSTAR, (uint64_t)Xsyscall);
wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32);
- wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C);
+ wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
if (full) {
wrmsr(MSR_FSBASE, 0);
Index: src/sys/arch/xen/conf/Makefile.xen
diff -u src/sys/arch/xen/conf/Makefile.xen:1.41 src/sys/arch/xen/conf/Makefile.xen:1.41.6.1
--- src/sys/arch/xen/conf/Makefile.xen:1.41 Thu Feb 2 19:09:08 2017
+++ src/sys/arch/xen/conf/Makefile.xen Wed Mar 7 14:50:57 2018
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.xen,v 1.41 2017/02/02 19:09:08 maxv Exp $
+# $NetBSD: Makefile.xen,v 1.41.6.1 2018/03/07 14:50:57 martin Exp $
# NetBSD: Makefile.i386,v 1.132 2003/07/05 16:56:10 simonb Exp
# Makefile for NetBSD
@@ -66,6 +66,9 @@ KERN_AS= obj
## (4) local objects, compile rules, and dependencies
##
MD_OBJS= locore.o spl.o copy.o vector.o
+.if ${XEN_BUILD} == amd64
+MD_OBJS+= amd64_trap.o
+.endif
MD_CFILES=
MD_SFILES= $S/arch/${XEN_BUILD}/${XEN_BUILD}/locore.S \
@@ -73,6 +76,10 @@ MD_SFILES= $S/arch/${XEN_BUILD}/${XEN_BU
$S/arch/${XEN_BUILD}/${XEN_BUILD}/vector.S \
$S/arch/${XEN_BUILD}/${XEN_BUILD}/copy.S
+.if ${XEN_BUILD} == amd64
+MD_SFILES+= $S/arch/${XEN_BUILD}/${XEN_BUILD}/amd64_trap.S
+.endif
+
copy.o: $S/arch/${XEN_BUILD}/${XEN_BUILD}/copy.S assym.h
${NORMAL_S}
@@ -84,6 +91,12 @@ spl.o: $S/arch/${XEN_BUILD}/${XEN_BUILD}
vector.o: $S/arch/${XEN_BUILD}/${XEN_BUILD}/vector.S assym.h
${NORMAL_S}
+
+.if ${XEN_BUILD} == amd64
+amd64_trap.o: $S/arch/${XEN_BUILD}/${XEN_BUILD}/amd64_trap.S assym.h
+ ${NORMAL_S}
+.endif
+
.ifndef noBEGIN
.if !make(obj) && !make(clean) && !make(cleandir)
.BEGIN:
