Module Name: src
Committed By: maya
Date: Wed Mar 7 15:52:43 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Move the hpcmips L1 cache disable hack up
where another machine-specific hacks exists.
Note that no existing kernel seems to enable this option.
To generate a diff of this commit:
cvs rdiff -u -r1.212 -r1.213 src/sys/arch/mips/mips/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/locore.S
diff -u src/sys/arch/mips/mips/locore.S:1.212 src/sys/arch/mips/mips/locore.S:1.213
--- src/sys/arch/mips/mips/locore.S:1.212 Wed Mar 7 15:49:45 2018
+++ src/sys/arch/mips/mips/locore.S Wed Mar 7 15:52:43 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.212 2018/03/07 15:49:45 maya Exp $ */
+/* $NetBSD: locore.S,v 1.213 2018/03/07 15:52:43 maya Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -63,7 +63,7 @@
#include <mips/trap.h>
#include <mips/locore.h>
-RCSID("$NetBSD: locore.S,v 1.212 2018/03/07 15:49:45 maya Exp $")
+RCSID("$NetBSD: locore.S,v 1.213 2018/03/07 15:52:43 maya Exp $")
#include "assym.h"
@@ -93,6 +93,15 @@ _C_LABEL(kernel_text):
mtc0 k0, MIPS_COP_0_STATUS
#endif
+#ifdef HPCMIPS_L1CACHE_DISABLE
+ mfc0 t0, MIPS_COP_0_CONFIG
+ li t1, 0xfffffff8
+ and t0, t0, t1
+ or t0, 0x00000002 # XXX, KSEG0 is uncached
+ mtc0 t0, MIPS_COP_0_CONFIG
+ COP0_SYNC
+#endif /* HPCMIPS_L1CACHE_DISABLE */
+
#ifdef MIPS64_OCTEON
//
// U-boot on the erlite starts all cpus at the kernel entry point.
@@ -145,14 +154,6 @@ _C_LABEL(kernel_text):
mtc0 t0, MIPS_COP_0_STATUS # the fp coprocessor
COP0_SYNC
#endif /* !emips */
-#ifdef HPCMIPS_L1CACHE_DISABLE
- mfc0 t0, MIPS_COP_0_CONFIG
- li t1, 0xfffffff8
- and t0, t0, t1
- or t0, 0x00000002 # XXX, KSEG0 is uncached
- mtc0 t0, MIPS_COP_0_CONFIG
- COP0_SYNC
-#endif /* HPCMIPS_L1CACHE_DISABLE */
#else /* NOFPU */
mfc0 t0, MIPS_COP_0_STATUS
MFC0_HAZARD
