Module Name: src
Committed By: msaitoh
Date: Mon Mar 12 07:35:45 UTC 2018
Modified Files:
src/sys/arch/x86/include: cacheinfo.h
Log Message:
AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.
To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/x86/include/cacheinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.25 src/sys/arch/x86/include/cacheinfo.h:1.26
--- src/sys/arch/x86/include/cacheinfo.h:1.25 Mon Mar 12 06:20:33 2018
+++ src/sys/arch/x86/include/cacheinfo.h Mon Mar 12 07:35:45 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.25 2018/03/12 06:20:33 msaitoh Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.26 2018/03/12 07:35:45 msaitoh Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -140,7 +140,7 @@ struct x86_cache_info {
/* L3 Cache */
#define AMD_L3_EDX_C_SIZE(x) ((((x) >> 18) & 0xffff) * 1024 * 512)
-#define AMD_L3_EDX_C_ASSOC(x) (((x) >> 12) & 0xff)
+#define AMD_L3_EDX_C_ASSOC(x) (((x) >> 12) & 0xf)
#define AMD_L3_EDX_C_LPT(x) (((x) >> 8) & 0xf)
#define AMD_L3_EDX_C_LS(x) ( (x) & 0xff)
