Module Name: src Committed By: maxv Date: Tue Mar 13 16:52:42 UTC 2018
Modified Files: src/sys/arch/x86/x86: patch.c Log Message: Fix wrong order; first enable WP, then enable interrupts. Otherwise we might get an interrupt before re-enabling WP, and be rescheduled as a result. In practice it never happens, because the previous PSL always has interrupts disabled too. To generate a diff of this commit: cvs rdiff -u -r1.33 -r1.34 src/sys/arch/x86/x86/patch.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/x86/x86/patch.c diff -u src/sys/arch/x86/x86/patch.c:1.33 src/sys/arch/x86/x86/patch.c:1.34 --- src/sys/arch/x86/x86/patch.c:1.33 Thu Feb 22 09:41:06 2018 +++ src/sys/arch/x86/x86/patch.c Tue Mar 13 16:52:42 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: patch.c,v 1.33 2018/02/22 09:41:06 maxv Exp $ */ +/* $NetBSD: patch.c,v 1.34 2018/03/13 16:52:42 maxv Exp $ */ /*- * Copyright (c) 2007, 2008, 2009 The NetBSD Foundation, Inc. @@ -34,7 +34,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: patch.c,v 1.33 2018/02/22 09:41:06 maxv Exp $"); +__KERNEL_RCSID(0, "$NetBSD: patch.c,v 1.34 2018/03/13 16:52:42 maxv Exp $"); #include "opt_lockdebug.h" #ifdef i386 @@ -182,10 +182,12 @@ x86_patch_window_close(u_long psl, u_lon /* Write back and invalidate cache, flush pipelines. */ wbinvd(); x86_flush(); - x86_write_psl(psl); /* Re-enable write protection. */ lcr0(cr0); + + /* Restore the PSL, potentially re-enabling interrupts. */ + x86_write_psl(psl); } void