Module Name: src
Committed By: msaitoh
Date: Tue Apr 10 08:18:38 UTC 2018
Modified Files:
src/sys/dev/pci: if_wmreg.h
Log Message:
SW PHY Config Enable bit for ICH8 B0 stepping is not bit 1 but bit 0.
To generate a diff of this commit:
cvs rdiff -u -r1.105 -r1.106 src/sys/dev/pci/if_wmreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/if_wmreg.h
diff -u src/sys/dev/pci/if_wmreg.h:1.105 src/sys/dev/pci/if_wmreg.h:1.106
--- src/sys/dev/pci/if_wmreg.h:1.105 Wed Nov 22 02:36:52 2017
+++ src/sys/dev/pci/if_wmreg.h Tue Apr 10 08:18:38 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wmreg.h,v 1.105 2017/11/22 02:36:52 msaitoh Exp $ */
+/* $NetBSD: if_wmreg.h,v 1.106 2018/04/10 08:18:38 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -590,8 +590,8 @@ struct livengood_tcpip_ctxdesc {
#define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */
#define WMREG_FEXTNVM 0x0028 /* Future Extended NVM register */
-#define FEXTNVM_SW_CONFIG __BIT(1)
-#define FEXTNVM_SW_CONFIG_ICH8M __BIT(27)
+#define FEXTNVM_SW_CONFIG __BIT(0) /* SW PHY Config En (ICH8 B0) */
+#define FEXTNVM_SW_CONFIG_ICH8M __BIT(27) /* SW PHY Config En (>= ICH8 B1) */
#define WMREG_FCAH 0x002c /* Flow Control Address High */
#define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */
