Module Name: src
Committed By: jmcneill
Date: Thu May 10 00:00:21 UTC 2018
Modified Files:
src/sys/arch/arm/sunxi: files.sunxi
Added Files:
src/sys/arch/arm/sunxi: sun50i_a64_acodec.c sun8i_codec.c sunxi_i2s.c
Log Message:
Add support for Allwinner A64 audio codec.
To generate a diff of this commit:
cvs rdiff -u -r1.54 -r1.55 src/sys/arch/arm/sunxi/files.sunxi
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/sunxi/sun50i_a64_acodec.c \
src/sys/arch/arm/sunxi/sun8i_codec.c src/sys/arch/arm/sunxi/sunxi_i2s.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/sunxi/files.sunxi
diff -u src/sys/arch/arm/sunxi/files.sunxi:1.54 src/sys/arch/arm/sunxi/files.sunxi:1.55
--- src/sys/arch/arm/sunxi/files.sunxi:1.54 Sun May 6 10:34:34 2018
+++ src/sys/arch/arm/sunxi/files.sunxi Thu May 10 00:00:21 2018
@@ -1,4 +1,4 @@
-# $NetBSD: files.sunxi,v 1.54 2018/05/06 10:34:34 jmcneill Exp $
+# $NetBSD: files.sunxi,v 1.55 2018/05/10 00:00:21 jmcneill Exp $
#
# Configuration info for Allwinner sunxi family SoCs
#
@@ -208,11 +208,26 @@ file arch/arm/sunxi/sunxi_codec.c sunxi
file arch/arm/sunxi/sun4i_a10_codec.c sunxi_codec
file arch/arm/sunxi/sun6i_a31_codec.c sunxi_codec
+# Audio codec (sun8i)
+device sun8icodec
+attach sun8icodec at fdt with sun8i_codec
+file arch/arm/sunxi/sun8i_codec.c sun8i_codec
+
# H3 Audio codec (analog part)
device h3codec
attach h3codec at fdt with h3_codec
file arch/arm/sunxi/sun8i_h3_codec.c h3_codec needs-flag
+# A64 Audio codec (analog part)
+device a64acodec
+attach a64acodec at fdt with a64_acodec
+file arch/arm/sunxi/sun50i_a64_acodec.c a64_acodec
+
+# I2S/PCM controller
+device sunxii2s: auconv, mulaw, aurateconv
+attach sunxii2s at fdt with sunxi_i2s
+file arch/arm/sunxi/sunxi_i2s.c sunxi_i2s
+
# Display controller
attach genfb at fdt with simplefb
file dev/fdt/simplefb.c simplefb
Added files:
Index: src/sys/arch/arm/sunxi/sun50i_a64_acodec.c
diff -u /dev/null src/sys/arch/arm/sunxi/sun50i_a64_acodec.c:1.1
--- /dev/null Thu May 10 00:00:21 2018
+++ src/sys/arch/arm/sunxi/sun50i_a64_acodec.c Thu May 10 00:00:21 2018
@@ -0,0 +1,483 @@
+/* $NetBSD: sun50i_a64_acodec.c,v 1.1 2018/05/10 00:00:21 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2018 Jared McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: sun50i_a64_acodec.c,v 1.1 2018/05/10 00:00:21 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+#include <sys/kmem.h>
+#include <sys/bitops.h>
+
+#include <dev/audio_dai.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#define A64_PR_CFG 0x00
+#define A64_AC_PR_RST __BIT(28)
+#define A64_AC_PR_RW __BIT(24)
+#define A64_AC_PR_ADDR __BITS(20,16)
+#define A64_ACDA_PR_WDAT __BITS(15,8)
+#define A64_ACDA_PR_RDAT __BITS(7,0)
+
+#define A64_HP_CTRL 0x00
+#define A64_HPPA_EN __BIT(6)
+#define A64_HPVOL __BITS(5,0)
+#define A64_OL_MIX_CTRL 0x01
+#define A64_LMIXMUTE_LDAC __BIT(1)
+#define A64_OR_MIX_CTRL 0x02
+#define A64_RMIXMUTE_RDAC __BIT(1)
+#define A64_LINEOUT_CTRL0 0x05
+#define A64_LINEOUT_LEFT_EN __BIT(7)
+#define A64_LINEOUT_RIGHT_EN __BIT(6)
+#define A64_LINEOUT_CTRL1 0x06
+#define A64_LINEOUT_VOL __BITS(4,0)
+#define A64_MIC1_CTRL 0x07
+#define A64_MIC1G __BITS(6,4)
+#define A64_MIC1AMPEN __BIT(3)
+#define A64_MIC1BOOST __BITS(2,0)
+#define A64_MIC2_CTRL 0x08
+#define A64_MIC2_SEL __BIT(7)
+#define A64_MIC2G __BITS(6,4)
+#define A64_MIC2AMPEN __BIT(3)
+#define A64_MIC2BOOST __BITS(2,0)
+#define A64_LINEIN_CTRL 0x09
+#define A64_LINEING __BITS(6,4)
+#define A64_MIX_DAC_CTRL 0x0a
+#define A64_DACAREN __BIT(7)
+#define A64_DACALEN __BIT(6)
+#define A64_RMIXEN __BIT(5)
+#define A64_LMIXEN __BIT(4)
+#define A64_RHPPAMUTE __BIT(3)
+#define A64_LHPPAMUTE __BIT(2)
+#define A64_RHPIS __BIT(1)
+#define A64_LHPIS __BIT(0)
+#define A64_L_ADCMIX_SRC 0x0b
+#define A64_R_ADCMIX_SRC 0x0c
+#define A64_ADCMIX_SRC_MIC1 __BIT(6)
+#define A64_ADCMIX_SRC_MIC2 __BIT(5)
+#define A64_ADCMIX_SRC_LINEIN __BIT(2)
+#define A64_ADCMIX_SRC_OMIXER __BIT(0)
+#define A64_ADC_CTRL 0x0d
+#define A64_ADCREN __BIT(7)
+#define A64_ADCLEN __BIT(6)
+#define A64_ADCG __BITS(2,0)
+
+struct a64_acodec_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ int sc_phandle;
+
+ struct audio_dai_device sc_dai;
+};
+
+enum a64_acodec_mixer_ctrl {
+ A64_CODEC_OUTPUT_CLASS,
+ A64_CODEC_INPUT_CLASS,
+ A64_CODEC_RECORD_CLASS,
+
+ A64_CODEC_OUTPUT_MASTER_VOLUME,
+ A64_CODEC_OUTPUT_HP_VOLUME,
+ A64_CODEC_INPUT_DAC_VOLUME,
+ A64_CODEC_INPUT_LINEIN_VOLUME,
+ A64_CODEC_INPUT_MIC1_VOLUME,
+ A64_CODEC_INPUT_MIC2_VOLUME,
+ A64_CODEC_RECORD_AGC_VOLUME,
+ A64_CODEC_RECORD_SOURCE,
+
+ A64_CODEC_MIXER_CTRL_LAST
+};
+
+static const struct a64_acodec_mixer {
+ const char * name;
+ enum a64_acodec_mixer_ctrl mixer_class;
+ u_int reg;
+ u_int mask;
+} a64_acodec_mixers[A64_CODEC_MIXER_CTRL_LAST] = {
+ [A64_CODEC_OUTPUT_MASTER_VOLUME] = { AudioNmaster,
+ A64_CODEC_OUTPUT_CLASS, A64_LINEOUT_CTRL1, A64_LINEOUT_VOL },
+ [A64_CODEC_OUTPUT_HP_VOLUME] = { AudioNheadphone,
+ A64_CODEC_OUTPUT_CLASS, A64_HP_CTRL, A64_HPVOL },
+ [A64_CODEC_INPUT_DAC_VOLUME] = { AudioNdac,
+ A64_CODEC_INPUT_CLASS, A64_LINEOUT_CTRL1, A64_LINEOUT_VOL },
+ [A64_CODEC_INPUT_LINEIN_VOLUME] = { AudioNline,
+ A64_CODEC_INPUT_CLASS, A64_LINEIN_CTRL, A64_LINEING },
+ [A64_CODEC_INPUT_MIC1_VOLUME] = { "mic1",
+ A64_CODEC_INPUT_CLASS, A64_MIC1_CTRL, A64_MIC1G },
+ [A64_CODEC_INPUT_MIC2_VOLUME] = { "mic2",
+ A64_CODEC_INPUT_CLASS, A64_MIC2_CTRL, A64_MIC2G },
+ [A64_CODEC_RECORD_AGC_VOLUME] = { AudioNagc,
+ A64_CODEC_RECORD_CLASS, A64_ADC_CTRL, A64_ADCG },
+};
+
+#define RD4(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+#define WR4(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+
+static u_int
+a64_acodec_pr_read(struct a64_acodec_softc *sc, u_int addr)
+{
+ uint32_t val;
+
+ /* Read current value */
+ val = RD4(sc, A64_PR_CFG);
+
+ /* De-assert reset */
+ val |= A64_AC_PR_RST;
+ WR4(sc, A64_PR_CFG, val);
+
+ /* Read mode */
+ val &= ~A64_AC_PR_RW;
+ WR4(sc, A64_PR_CFG, val);
+
+ /* Set address */
+ val &= ~A64_AC_PR_ADDR;
+ val |= __SHIFTIN(addr, A64_AC_PR_ADDR);
+ WR4(sc, A64_PR_CFG, val);
+
+ /* Read data */
+ return __SHIFTOUT(RD4(sc, A64_PR_CFG), A64_ACDA_PR_RDAT);
+}
+
+static void
+a64_acodec_pr_write(struct a64_acodec_softc *sc, u_int addr, u_int data)
+{
+ uint32_t val;
+
+ /* Read current value */
+ val = RD4(sc, A64_PR_CFG);
+
+ /* De-assert reset */
+ val |= A64_AC_PR_RST;
+ WR4(sc, A64_PR_CFG, val);
+
+ /* Set address */
+ val &= ~A64_AC_PR_ADDR;
+ val |= __SHIFTIN(addr, A64_AC_PR_ADDR);
+ WR4(sc, A64_PR_CFG, val);
+
+ /* Write data */
+ val &= ~A64_ACDA_PR_WDAT;
+ val |= __SHIFTIN(data, A64_ACDA_PR_WDAT);
+ WR4(sc, A64_PR_CFG, val);
+
+ /* Write mode */
+ val |= A64_AC_PR_RW;
+ WR4(sc, A64_PR_CFG, val);
+
+ /* Clear write mode */
+ val &= ~A64_AC_PR_RW;
+ WR4(sc, A64_PR_CFG, val);
+}
+
+static void
+a64_acodec_pr_set_clear(struct a64_acodec_softc *sc, u_int addr, u_int set, u_int clr)
+{
+ u_int old, new;
+
+ old = a64_acodec_pr_read(sc, addr);
+ new = set | (old & ~clr);
+ a64_acodec_pr_write(sc, addr, new);
+}
+
+static int
+a64_acodec_trigger_output(void *priv, void *start, void *end, int blksize,
+ void (*intr)(void *), void *intrarg, const audio_params_t *params)
+{
+ struct a64_acodec_softc * const sc = priv;
+
+ /* Enable DAC analog l/r channels and output mixer */
+ a64_acodec_pr_set_clear(sc, A64_MIX_DAC_CTRL,
+ A64_DACAREN | A64_DACALEN | A64_RMIXEN | A64_LMIXEN, 0);
+ /* Unmute DAC l/r channels to output mixer */
+ a64_acodec_pr_set_clear(sc, A64_OL_MIX_CTRL,
+ A64_LMIXMUTE_LDAC, 0);
+ a64_acodec_pr_set_clear(sc, A64_OR_MIX_CTRL,
+ A64_RMIXMUTE_RDAC, 0);
+
+ return 0;
+}
+
+static int
+a64_acodec_trigger_input(void *priv, void *start, void *end, int blksize,
+ void (*intr)(void *), void *intrarg, const audio_params_t *params)
+{
+ struct a64_acodec_softc * const sc = priv;
+
+ /* Enable ADC analog l/r channels */
+ a64_acodec_pr_set_clear(sc, A64_ADC_CTRL,
+ A64_ADCREN | A64_ADCLEN, 0);
+
+ return 0;
+}
+
+static int
+a64_acodec_halt_output(void *priv)
+{
+ struct a64_acodec_softc * const sc = priv;
+
+ /* Mute DAC l/r channels to output mixer */
+ a64_acodec_pr_set_clear(sc, A64_OL_MIX_CTRL,
+ 0, A64_LMIXMUTE_LDAC);
+ a64_acodec_pr_set_clear(sc, A64_OR_MIX_CTRL,
+ 0, A64_RMIXMUTE_RDAC);
+ /* Disable DAC analog l/r channels and output mixer */
+ a64_acodec_pr_set_clear(sc, A64_MIX_DAC_CTRL,
+ 0, A64_DACAREN | A64_DACALEN | A64_RMIXEN | A64_LMIXEN);
+
+ return 0;
+}
+
+static int
+a64_acodec_halt_input(void *priv)
+{
+ struct a64_acodec_softc * const sc = priv;
+
+ /* Disable ADC analog l/r channels */
+ a64_acodec_pr_set_clear(sc, A64_ADC_CTRL,
+ 0, A64_ADCREN | A64_ADCLEN);
+
+ return 0;
+}
+
+static int
+a64_acodec_set_port(void *priv, mixer_ctrl_t *mc)
+{
+ struct a64_acodec_softc * const sc = priv;
+ const struct a64_acodec_mixer *mix;
+ u_int val, shift;
+ int nvol;
+
+ switch (mc->dev) {
+ case A64_CODEC_OUTPUT_MASTER_VOLUME:
+ case A64_CODEC_OUTPUT_HP_VOLUME:
+ case A64_CODEC_INPUT_DAC_VOLUME:
+ case A64_CODEC_INPUT_LINEIN_VOLUME:
+ case A64_CODEC_INPUT_MIC1_VOLUME:
+ case A64_CODEC_INPUT_MIC2_VOLUME:
+ case A64_CODEC_RECORD_AGC_VOLUME:
+ mix = &a64_acodec_mixers[mc->dev];
+ val = a64_acodec_pr_read(sc, mix->reg);
+ shift = 8 - fls32(__SHIFTOUT_MASK(mix->mask));
+ nvol = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> shift;
+ val &= ~mix->mask;
+ val |= __SHIFTIN(nvol, mix->mask);
+ a64_acodec_pr_write(sc, mix->reg, val);
+ return 0;
+
+ case A64_CODEC_RECORD_SOURCE:
+ a64_acodec_pr_write(sc, A64_L_ADCMIX_SRC, mc->un.mask);
+ a64_acodec_pr_write(sc, A64_R_ADCMIX_SRC, mc->un.mask);
+ return 0;
+ }
+
+ return ENXIO;
+}
+
+static int
+a64_acodec_get_port(void *priv, mixer_ctrl_t *mc)
+{
+ struct a64_acodec_softc * const sc = priv;
+ const struct a64_acodec_mixer *mix;
+ u_int val, shift;
+ int nvol;
+
+ switch (mc->dev) {
+ case A64_CODEC_OUTPUT_MASTER_VOLUME:
+ case A64_CODEC_OUTPUT_HP_VOLUME:
+ case A64_CODEC_INPUT_DAC_VOLUME:
+ case A64_CODEC_INPUT_LINEIN_VOLUME:
+ case A64_CODEC_INPUT_MIC1_VOLUME:
+ case A64_CODEC_INPUT_MIC2_VOLUME:
+ case A64_CODEC_RECORD_AGC_VOLUME:
+ mix = &a64_acodec_mixers[mc->dev];
+ val = a64_acodec_pr_read(sc, mix->reg);
+ shift = 8 - fls32(__SHIFTOUT_MASK(mix->mask));
+ nvol = __SHIFTOUT(val, mix->mask) << shift;
+ mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = nvol;
+ mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = nvol;
+ return 0;
+
+ case A64_CODEC_RECORD_SOURCE:
+ mc->un.mask =
+ a64_acodec_pr_read(sc, A64_L_ADCMIX_SRC) |
+ a64_acodec_pr_read(sc, A64_R_ADCMIX_SRC);
+ return 0;
+ }
+
+ return ENXIO;
+}
+
+static int
+a64_acodec_query_devinfo(void *priv, mixer_devinfo_t *di)
+{
+ const struct a64_acodec_mixer *mix;
+
+ switch (di->index) {
+ case A64_CODEC_OUTPUT_CLASS:
+ di->mixer_class = di->index;
+ strcpy(di->label.name, AudioCoutputs);
+ di->type = AUDIO_MIXER_CLASS;
+ di->next = di->prev = AUDIO_MIXER_LAST;
+ return 0;
+
+ case A64_CODEC_INPUT_CLASS:
+ di->mixer_class = di->index;
+ strcpy(di->label.name, AudioCinputs);
+ di->type = AUDIO_MIXER_CLASS;
+ di->next = di->prev = AUDIO_MIXER_LAST;
+ return 0;
+
+ case A64_CODEC_RECORD_CLASS:
+ di->mixer_class = di->index;
+ strcpy(di->label.name, AudioCrecord);
+ di->type = AUDIO_MIXER_CLASS;
+ di->next = di->prev = AUDIO_MIXER_LAST;
+ return 0;
+
+ case A64_CODEC_OUTPUT_MASTER_VOLUME:
+ case A64_CODEC_OUTPUT_HP_VOLUME:
+ case A64_CODEC_INPUT_DAC_VOLUME:
+ case A64_CODEC_INPUT_LINEIN_VOLUME:
+ case A64_CODEC_INPUT_MIC1_VOLUME:
+ case A64_CODEC_INPUT_MIC2_VOLUME:
+ case A64_CODEC_RECORD_AGC_VOLUME:
+ mix = &a64_acodec_mixers[di->index];
+ di->mixer_class = mix->mixer_class;
+ strcpy(di->label.name, mix->name);
+ di->un.v.delta =
+ 256 / (__SHIFTOUT_MASK(mix->mask) + 1);
+ di->type = AUDIO_MIXER_VALUE;
+ di->next = di->prev = AUDIO_MIXER_LAST;
+ di->un.v.num_channels = 2;
+ strcpy(di->un.v.units.name, AudioNvolume);
+ return 0;
+
+ case A64_CODEC_RECORD_SOURCE:
+ di->mixer_class = A64_CODEC_RECORD_CLASS;
+ strcpy(di->label.name, AudioNsource);
+ di->type = AUDIO_MIXER_SET;
+ di->next = di->prev = AUDIO_MIXER_LAST;
+ di->un.s.num_mem = 4;
+ strcpy(di->un.s.member[0].label.name, AudioNline);
+ di->un.s.member[0].mask = A64_ADCMIX_SRC_LINEIN;
+ strcpy(di->un.s.member[1].label.name, "mic1");
+ di->un.s.member[1].mask = A64_ADCMIX_SRC_MIC1;
+ strcpy(di->un.s.member[2].label.name, "mic2");
+ di->un.s.member[2].mask = A64_ADCMIX_SRC_MIC2;
+ strcpy(di->un.s.member[3].label.name, AudioNdac);
+ di->un.s.member[3].mask = A64_ADCMIX_SRC_OMIXER;
+ return 0;
+
+ }
+
+ return ENXIO;
+}
+
+static const struct audio_hw_if a64_acodec_hw_if = {
+ .trigger_output = a64_acodec_trigger_output,
+ .trigger_input = a64_acodec_trigger_input,
+ .halt_output = a64_acodec_halt_output,
+ .halt_input = a64_acodec_halt_input,
+ .set_port = a64_acodec_set_port,
+ .get_port = a64_acodec_get_port,
+ .query_devinfo = a64_acodec_query_devinfo,
+};
+
+static audio_dai_tag_t
+a64_acodec_dai_get_tag(device_t dev, const void *data, size_t len)
+{
+ struct a64_acodec_softc * const sc = device_private(dev);
+
+ if (len != 4)
+ return NULL;
+
+ return &sc->sc_dai;
+}
+
+static struct fdtbus_dai_controller_func a64_acodec_dai_funcs = {
+ .get_tag = a64_acodec_dai_get_tag
+};
+
+static const char * compatible[] = {
+ "allwinner,sun50i-a64-codec-analog",
+ NULL
+};
+
+static int
+a64_acodec_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+a64_acodec_attach(device_t parent, device_t self, void *aux)
+{
+ struct a64_acodec_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ bus_addr_t addr;
+ bus_size_t size;
+
+ sc->sc_dev = self;
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+ sc->sc_bst = faa->faa_bst;
+ if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
+ aprint_error(": couldn't map registers\n");
+ return;
+ }
+
+ sc->sc_phandle = phandle;
+
+ aprint_naive("\n");
+ aprint_normal(": A64 Audio Codec (analog part)\n");
+
+ /* Right & Left LINEOUT enable */
+ a64_acodec_pr_set_clear(sc, A64_LINEOUT_CTRL0,
+ A64_LINEOUT_LEFT_EN | A64_LINEOUT_RIGHT_EN, 0);
+ /* Right & Left Headphone PA enable */
+ a64_acodec_pr_set_clear(sc, A64_HP_CTRL,
+ A64_HPPA_EN, 0);
+
+ sc->sc_dai.dai_hw_if = &a64_acodec_hw_if;
+ sc->sc_dai.dai_dev = self;
+ sc->sc_dai.dai_priv = sc;
+ fdtbus_register_dai_controller(self, phandle, &a64_acodec_dai_funcs);
+}
+
+CFATTACH_DECL_NEW(a64_acodec, sizeof(struct a64_acodec_softc),
+ a64_acodec_match, a64_acodec_attach, NULL, NULL);
Index: src/sys/arch/arm/sunxi/sun8i_codec.c
diff -u /dev/null src/sys/arch/arm/sunxi/sun8i_codec.c:1.1
--- /dev/null Thu May 10 00:00:21 2018
+++ src/sys/arch/arm/sunxi/sun8i_codec.c Thu May 10 00:00:21 2018
@@ -0,0 +1,312 @@
+/* $NetBSD: sun8i_codec.c,v 1.1 2018/05/10 00:00:21 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2018 Jared McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: sun8i_codec.c,v 1.1 2018/05/10 00:00:21 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+#include <sys/kmem.h>
+#include <sys/bitops.h>
+#include <sys/gpio.h>
+
+#include <dev/audio_dai.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#define SYSCLK_CTL 0x00c
+#define AIF1CLK_ENA __BIT(11)
+#define AIF1CLK_SRC __BITS(9,8)
+#define AIF1CLK_SRC_PLL 2
+#define SYSCLK_ENA __BIT(3)
+#define SYSCLK_SRC __BIT(0)
+
+#define MOD_CLK_ENA 0x010
+#define MOD_RST_CTL 0x014
+#define MOD_AIF1 __BIT(15)
+#define MOD_ADC __BIT(3)
+#define MOD_DAC __BIT(2)
+
+#define SYS_SR_CTRL 0x018
+#define AIF1_FS __BITS(15,12)
+#define AIF_FS_48KHZ 8
+
+#define AIF1CLK_CTRL 0x040
+#define AIF1_MSTR_MOD __BIT(15)
+#define AIF1_BCLK_INV __BIT(14)
+#define AIF1_LRCK_INV __BIT(13)
+#define AIF1_BCLK_DIV __BITS(12,9)
+#define AIF1_BCLK_DIV_16 6
+#define AIF1_LRCK_DIV __BITS(8,6)
+#define AIF1_LRCK_DIV_16 0
+#define AIF1_LRCK_DIV_64 2
+#define AIF1_WORD_SIZ __BITS(5,4)
+#define AIF1_WORD_SIZ_16 1
+#define AIF1_DATA_FMT __BITS(3,2)
+#define AIF1_DATA_FMT_I2S 0
+#define AIF1_DATA_FMT_LJ 1
+#define AIF1_DATA_FMT_RJ 2
+#define AIF1_DATA_FMT_DSP 3
+
+#define AIF1_DACDAT_CTRL 0x048
+#define AIF1_DAC0L_ENA __BIT(15)
+#define AIF1_DAC0R_ENA __BIT(14)
+
+#define ADC_DIG_CTRL 0x100
+#define ADC_DIG_CTRL_ENAD __BIT(15)
+
+#define DAC_DIG_CTRL 0x120
+#define DAC_DIG_CTRL_ENDA __BIT(15)
+
+#define DAC_MXR_SRC 0x130
+#define DACL_MXR_SRC __BITS(15,12)
+#define DACL_MXR_SRC_AIF1_DAC0L 0x8
+#define DACR_MXR_SRC __BITS(11,8)
+#define DACR_MXR_SRC_AIF1_DAC0R 0x8
+
+struct sun8i_codec_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ int sc_phandle;
+
+ struct audio_dai_device sc_dai;
+
+ struct fdtbus_gpio_pin *sc_pin_pa;
+
+ struct clk *sc_clk_gate;
+ struct clk *sc_clk_mod;
+};
+
+#define RD4(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+#define WR4(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+
+static int
+sun8i_codec_set_params(void *priv, int setmode, int usemode,
+ audio_params_t *play, audio_params_t *rec,
+ stream_filter_list_t *pfil, stream_filter_list_t *rfil)
+{
+ if (play && (setmode & AUMODE_PLAY))
+ if (play->sample_rate != 48000)
+ return EINVAL;
+
+ if (rec && (setmode & AUMODE_RECORD))
+ if (rec->sample_rate != 48000)
+ return EINVAL;
+
+ return 0;
+}
+
+static const struct audio_hw_if sun8i_codec_hw_if = {
+ .set_params = sun8i_codec_set_params,
+};
+
+static audio_dai_tag_t
+sun8i_codec_dai_get_tag(device_t dev, const void *data, size_t len)
+{
+ struct sun8i_codec_softc * const sc = device_private(dev);
+
+ if (len != 4)
+ return NULL;
+
+ return &sc->sc_dai;
+}
+
+static struct fdtbus_dai_controller_func sun8i_codec_dai_funcs = {
+ .get_tag = sun8i_codec_dai_get_tag
+};
+
+static int
+sun8i_codec_dai_set_format(audio_dai_tag_t dai, u_int format)
+{
+ struct sun8i_codec_softc * const sc = audio_dai_private(dai);
+ uint32_t val;
+
+ const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK);
+ const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK);
+ const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK);
+
+ val = RD4(sc, AIF1CLK_CTRL);
+
+ val &= ~AIF1_DATA_FMT;
+ switch (fmt) {
+ case AUDIO_DAI_FORMAT_I2S:
+ val |= __SHIFTIN(AIF1_DATA_FMT_I2S, AIF1_DATA_FMT);
+ break;
+ case AUDIO_DAI_FORMAT_RJ:
+ val |= __SHIFTIN(AIF1_DATA_FMT_RJ, AIF1_DATA_FMT);
+ break;
+ case AUDIO_DAI_FORMAT_LJ:
+ val |= __SHIFTIN(AIF1_DATA_FMT_LJ, AIF1_DATA_FMT);
+ break;
+ case AUDIO_DAI_FORMAT_DSPA:
+ case AUDIO_DAI_FORMAT_DSPB:
+ val |= __SHIFTIN(AIF1_DATA_FMT_DSP, AIF1_DATA_FMT);
+ break;
+ default:
+ return EINVAL;
+ }
+
+ val &= ~(AIF1_BCLK_INV|AIF1_LRCK_INV);
+ /* Codec LRCK polarity is inverted (datasheet is wrong) */
+ if (!AUDIO_DAI_POLARITY_F(pol))
+ val |= AIF1_LRCK_INV;
+ if (AUDIO_DAI_POLARITY_B(pol))
+ val |= AIF1_BCLK_INV;
+
+ switch (clk) {
+ case AUDIO_DAI_CLOCK_CBM_CFM:
+ val &= ~AIF1_MSTR_MOD; /* codec is master */
+ break;
+ case AUDIO_DAI_CLOCK_CBS_CFS:
+ val |= AIF1_MSTR_MOD; /* codec is slave */
+ break;
+ default:
+ return EINVAL;
+ }
+
+ val &= ~AIF1_LRCK_DIV;
+ val |= __SHIFTIN(AIF1_LRCK_DIV_64, AIF1_LRCK_DIV);
+
+ val &= ~AIF1_BCLK_DIV;
+ val |= __SHIFTIN(AIF1_BCLK_DIV_16, AIF1_BCLK_DIV);
+
+ WR4(sc, AIF1CLK_CTRL, val);
+
+ return 0;
+}
+
+static const char * compatible[] = {
+ "allwinner,sun50i-a64-codec",
+ NULL
+};
+
+static int
+sun8i_codec_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+sun8i_codec_attach(device_t parent, device_t self, void *aux)
+{
+ struct sun8i_codec_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ bus_addr_t addr;
+ bus_size_t size;
+ uint32_t val;
+
+ sc->sc_dev = self;
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+ sc->sc_bst = faa->faa_bst;
+ if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
+ aprint_error(": couldn't map registers\n");
+ return;
+ }
+
+ sc->sc_clk_gate = fdtbus_clock_get(phandle, "bus");
+ sc->sc_clk_mod = fdtbus_clock_get(phandle, "mod");
+ if (!sc->sc_clk_gate || !sc->sc_clk_mod) {
+ aprint_error(": couldn't get clocks\n");
+ return;
+ }
+ if (clk_enable(sc->sc_clk_gate) != 0) {
+ aprint_error(": couldn't enable bus clock\n");
+ return;
+ }
+
+ sc->sc_phandle = phandle;
+
+ aprint_naive("\n");
+ aprint_normal(": Audio Codec\n");
+
+ /* Enable clocks */
+ val = RD4(sc, SYSCLK_CTL);
+ val |= AIF1CLK_ENA;
+ val &= ~AIF1CLK_SRC;
+ val |= __SHIFTIN(AIF1CLK_SRC_PLL, AIF1CLK_SRC);
+ val |= SYSCLK_ENA;
+ val &= ~SYSCLK_SRC;
+ WR4(sc, SYSCLK_CTL, val);
+ WR4(sc, MOD_CLK_ENA, MOD_AIF1 | MOD_ADC | MOD_DAC);
+ WR4(sc, MOD_RST_CTL, MOD_AIF1 | MOD_ADC | MOD_DAC);
+
+ /* Enable digital parts */
+ WR4(sc, DAC_DIG_CTRL, DAC_DIG_CTRL_ENDA);
+ WR4(sc, ADC_DIG_CTRL, ADC_DIG_CTRL_ENAD);
+
+ /* Set AIF1 to 48 kHz */
+ val = RD4(sc, SYS_SR_CTRL);
+ val &= ~AIF1_FS;
+ val |= __SHIFTIN(AIF_FS_48KHZ, AIF1_FS);
+ WR4(sc, SYS_SR_CTRL, val);
+
+ /* Set AIF1 to 16-bit */
+ val = RD4(sc, AIF1CLK_CTRL);
+ val &= ~AIF1_WORD_SIZ;
+ val |= __SHIFTIN(AIF1_WORD_SIZ_16, AIF1_WORD_SIZ);
+ WR4(sc, AIF1CLK_CTRL, val);
+
+ /* Enable AIF1 DAC timelot 0 */
+ val = RD4(sc, AIF1_DACDAT_CTRL);
+ val |= AIF1_DAC0L_ENA;
+ val |= AIF1_DAC0R_ENA;
+ WR4(sc, AIF1_DACDAT_CTRL, val);
+
+ /* DAC mixer source select */
+ val = RD4(sc, DAC_MXR_SRC);
+ val &= ~DACL_MXR_SRC;
+ val |= __SHIFTIN(DACL_MXR_SRC_AIF1_DAC0L, DACL_MXR_SRC);
+ val &= ~DACR_MXR_SRC;
+ val |= __SHIFTIN(DACR_MXR_SRC_AIF1_DAC0R, DACR_MXR_SRC);
+ WR4(sc, DAC_MXR_SRC, val);
+
+ /* Enable PA power */
+ sc->sc_pin_pa = fdtbus_gpio_acquire(phandle, "allwinner,pa-gpios", GPIO_PIN_OUTPUT);
+ if (sc->sc_pin_pa)
+ fdtbus_gpio_write(sc->sc_pin_pa, 1);
+
+ sc->sc_dai.dai_set_format = sun8i_codec_dai_set_format;
+ sc->sc_dai.dai_hw_if = &sun8i_codec_hw_if;
+ sc->sc_dai.dai_dev = self;
+ sc->sc_dai.dai_priv = sc;
+ fdtbus_register_dai_controller(self, phandle, &sun8i_codec_dai_funcs);
+}
+
+CFATTACH_DECL_NEW(sun8i_codec, sizeof(struct sun8i_codec_softc),
+ sun8i_codec_match, sun8i_codec_attach, NULL, NULL);
Index: src/sys/arch/arm/sunxi/sunxi_i2s.c
diff -u /dev/null src/sys/arch/arm/sunxi/sunxi_i2s.c:1.1
--- /dev/null Thu May 10 00:00:21 2018
+++ src/sys/arch/arm/sunxi/sunxi_i2s.c Thu May 10 00:00:21 2018
@@ -0,0 +1,827 @@
+/* $NetBSD: sunxi_i2s.c,v 1.1 2018/05/10 00:00:21 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2018 Jared McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: sunxi_i2s.c,v 1.1 2018/05/10 00:00:21 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+#include <sys/kmem.h>
+#include <sys/gpio.h>
+
+#include <sys/audioio.h>
+#include <dev/audio_if.h>
+#include <dev/auconv.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#define SUNXI_I2S_CLK_RATE 24576000
+
+#define DA_CTL 0x00
+#define DA_CTL_SDO_EN __BIT(8)
+#define DA_CTL_MS __BIT(5)
+#define DA_CTL_PCM __BIT(4)
+#define DA_CTL_TXEN __BIT(2)
+#define DA_CTL_RXEN __BIT(1)
+#define DA_CTL_GEN __BIT(0)
+#define DA_FAT0 0x04
+#define DA_FAT0_LRCP __BIT(7)
+#define DA_LRCP_NORMAL 0
+#define DA_LRCP_INVERTED 1
+#define DA_FAT0_BCP __BIT(6)
+#define DA_BCP_NORMAL 0
+#define DA_BCP_INVERTED 1
+#define DA_FAT0_SR __BITS(5,4)
+#define DA_FAT0_WSS __BITS(3,2)
+#define DA_FAT0_FMT __BITS(1,0)
+#define DA_FMT_I2S 0
+#define DA_FMT_LJ 1
+#define DA_FMT_RJ 2
+#define DA_FAT1 0x08
+#define DA_ISTA 0x0c
+#define DA_RXFIFO 0x10
+#define DA_FCTL 0x14
+#define DA_FCTL_HUB_EN __BIT(31)
+#define DA_FCTL_FTX __BIT(25)
+#define DA_FCTL_FRX __BIT(24)
+#define DA_FSTA 0x18
+#define DA_INT 0x1c
+#define DA_INT_TX_DRQ __BIT(7)
+#define DA_INT_RX_DRQ __BIT(3)
+#define DA_TXFIFO 0x20
+#define DA_CLKD 0x24
+#define DA_CLKD_MCLKO_EN __BIT(7)
+#define DA_CLKD_BCLKDIV __BITS(6,4)
+#define DA_CLKD_BCLKDIV_16 5
+#define DA_CLKD_MCLKDIV __BITS(3,0)
+#define DA_CLKD_MCLKDIV_1 0
+#define DA_TXCNT 0x28
+#define DA_RXCNT 0x2c
+
+#define DA_CHSEL_EN __BITS(11,4)
+#define DA_CHSEL_SEL __BITS(2,0)
+
+struct sunxi_i2s_config {
+ const char *name;
+ bus_size_t txchsel;
+ bus_size_t txchmap;
+ bus_size_t rxchsel;
+ bus_size_t rxchmap;
+};
+
+static const struct sunxi_i2s_config sun50i_a64_codec_config = {
+ .name = "Audio Codec (digital part)",
+ .txchsel = 0x30,
+ .txchmap = 0x34,
+ .rxchsel = 0x38,
+ .rxchmap = 0x3c,
+};
+
+static const struct of_compat_data compat_data[] = {
+ { "allwinner,sun50i-a64-acodec-i2s",
+ (uintptr_t)&sun50i_a64_codec_config },
+
+ { NULL }
+};
+
+struct sunxi_i2s_softc;
+
+struct sunxi_i2s_chan {
+ struct sunxi_i2s_softc *ch_sc;
+ u_int ch_mode;
+
+ struct fdtbus_dma *ch_dma;
+ struct fdtbus_dma_req ch_req;
+
+ audio_params_t ch_params;
+
+ bus_addr_t ch_start_phys;
+ bus_addr_t ch_end_phys;
+ bus_addr_t ch_cur_phys;
+ int ch_blksize;
+
+ void (*ch_intr)(void *);
+ void *ch_intrarg;
+};
+
+struct sunxi_i2s_dma {
+ LIST_ENTRY(sunxi_i2s_dma) dma_list;
+ bus_dmamap_t dma_map;
+ void *dma_addr;
+ size_t dma_size;
+ bus_dma_segment_t dma_segs[1];
+ int dma_nsegs;
+};
+
+struct sunxi_i2s_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ bus_dma_tag_t sc_dmat;
+ int sc_phandle;
+ bus_addr_t sc_baseaddr;
+
+ struct sunxi_i2s_config *sc_cfg;
+
+ LIST_HEAD(, sunxi_i2s_dma) sc_dmalist;
+
+ kmutex_t sc_lock;
+ kmutex_t sc_intr_lock;
+
+ struct audio_format sc_format;
+ struct audio_encoding_set *sc_encodings;
+
+ struct sunxi_i2s_chan sc_pchan;
+ struct sunxi_i2s_chan sc_rchan;
+
+ struct audio_dai_device sc_dai;
+};
+
+#define I2S_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+#define I2S_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+
+static int
+sunxi_i2s_allocdma(struct sunxi_i2s_softc *sc, size_t size,
+ size_t align, struct sunxi_i2s_dma *dma)
+{
+ int error;
+
+ dma->dma_size = size;
+ error = bus_dmamem_alloc(sc->sc_dmat, dma->dma_size, align, 0,
+ dma->dma_segs, 1, &dma->dma_nsegs, BUS_DMA_WAITOK);
+ if (error)
+ return error;
+
+ error = bus_dmamem_map(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs,
+ dma->dma_size, &dma->dma_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
+ if (error)
+ goto free;
+
+ error = bus_dmamap_create(sc->sc_dmat, dma->dma_size, dma->dma_nsegs,
+ dma->dma_size, 0, BUS_DMA_WAITOK, &dma->dma_map);
+ if (error)
+ goto unmap;
+
+ error = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_addr,
+ dma->dma_size, NULL, BUS_DMA_WAITOK);
+ if (error)
+ goto destroy;
+
+ return 0;
+
+destroy:
+ bus_dmamap_destroy(sc->sc_dmat, dma->dma_map);
+unmap:
+ bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size);
+free:
+ bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs);
+
+ return error;
+}
+
+static void
+sunxi_i2s_freedma(struct sunxi_i2s_softc *sc, struct sunxi_i2s_dma *dma)
+{
+ bus_dmamap_unload(sc->sc_dmat, dma->dma_map);
+ bus_dmamap_destroy(sc->sc_dmat, dma->dma_map);
+ bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size);
+ bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs);
+}
+
+static int
+sunxi_i2s_transfer(struct sunxi_i2s_chan *ch)
+{
+ bus_dma_segment_t seg;
+
+ seg.ds_addr = ch->ch_cur_phys;
+ seg.ds_len = ch->ch_blksize;
+ ch->ch_req.dreq_segs = &seg;
+ ch->ch_req.dreq_nsegs = 1;
+
+ return fdtbus_dma_transfer(ch->ch_dma, &ch->ch_req);
+}
+
+static int
+sunxi_i2s_open(void *priv, int flags)
+{
+ return 0;
+}
+
+static void
+sunxi_i2s_close(void *priv)
+{
+}
+
+static int
+sunxi_i2s_query_encoding(void *priv, struct audio_encoding *ae)
+{
+ struct sunxi_i2s_softc * const sc = priv;
+
+ return auconv_query_encoding(sc->sc_encodings, ae);
+}
+
+static int
+sunxi_i2s_set_params(void *priv, int setmode, int usemode,
+ audio_params_t *play, audio_params_t *rec,
+ stream_filter_list_t *pfil, stream_filter_list_t *rfil)
+{
+ struct sunxi_i2s_softc * const sc = priv;
+ int index;
+
+ if (play && (setmode & AUMODE_PLAY)) {
+ index = auconv_set_converter(&sc->sc_format, 1,
+ AUMODE_PLAY, play, true, pfil);
+ if (index < 0)
+ return EINVAL;
+ sc->sc_pchan.ch_params = pfil->req_size > 0 ?
+ pfil->filters[0].param : *play;
+ }
+ if (rec && (setmode & AUMODE_RECORD)) {
+ index = auconv_set_converter(&sc->sc_format, 1,
+ AUMODE_RECORD, rec, true, rfil);
+ if (index < 0)
+ return EINVAL;
+ sc->sc_rchan.ch_params = rfil->req_size > 0 ?
+ rfil->filters[0].param : *rec;
+ }
+
+ return 0;
+}
+
+static void *
+sunxi_i2s_allocm(void *priv, int dir, size_t size)
+{
+ struct sunxi_i2s_softc * const sc = priv;
+ struct sunxi_i2s_dma *dma;
+ int error;
+
+ dma = kmem_alloc(sizeof(*dma), KM_SLEEP);
+
+ error = sunxi_i2s_allocdma(sc, size, 16, dma);
+ if (error) {
+ kmem_free(dma, sizeof(*dma));
+ device_printf(sc->sc_dev, "couldn't allocate DMA memory (%d)\n",
+ error);
+ return NULL;
+ }
+
+ LIST_INSERT_HEAD(&sc->sc_dmalist, dma, dma_list);
+
+ return dma->dma_addr;
+}
+
+static void
+sunxi_i2s_freem(void *priv, void *addr, size_t size)
+{
+ struct sunxi_i2s_softc * const sc = priv;
+ struct sunxi_i2s_dma *dma;
+
+ LIST_FOREACH(dma, &sc->sc_dmalist, dma_list)
+ if (dma->dma_addr == addr) {
+ sunxi_i2s_freedma(sc, dma);
+ LIST_REMOVE(dma, dma_list);
+ kmem_free(dma, sizeof(*dma));
+ break;
+ }
+}
+
+static paddr_t
+sunxi_i2s_mappage(void *priv, void *addr, off_t off, int prot)
+{
+ struct sunxi_i2s_softc * const sc = priv;
+ struct sunxi_i2s_dma *dma;
+
+ if (off < 0)
+ return -1;
+
+ LIST_FOREACH(dma, &sc->sc_dmalist, dma_list)
+ if (dma->dma_addr == addr) {
+ return bus_dmamem_mmap(sc->sc_dmat, dma->dma_segs,
+ dma->dma_nsegs, off, prot, BUS_DMA_WAITOK);
+ }
+
+ return -1;
+}
+
+static int
+sunxi_i2s_get_props(void *priv)
+{
+ return AUDIO_PROP_PLAYBACK|AUDIO_PROP_CAPTURE|
+ AUDIO_PROP_MMAP|AUDIO_PROP_FULLDUPLEX;
+}
+
+static int
+sunxi_i2s_round_blocksize(void *priv, int bs, int mode,
+ const audio_params_t *params)
+{
+ bs &= ~3;
+ if (bs == 0)
+ bs = 4;
+ return bs;
+}
+
+static size_t
+sunxi_i2s_round_buffersize(void *priv, int dir, size_t bufsize)
+{
+ return bufsize;
+}
+
+static int
+sunxi_i2s_trigger_output(void *priv, void *start, void *end, int blksize,
+ void (*intr)(void *), void *intrarg, const audio_params_t *params)
+{
+ struct sunxi_i2s_softc * const sc = priv;
+ struct sunxi_i2s_chan *ch = &sc->sc_pchan;
+ struct sunxi_i2s_dma *dma;
+ bus_addr_t pstart;
+ bus_size_t psize;
+ uint32_t val;
+ int error;
+
+ pstart = 0;
+ psize = (uintptr_t)end - (uintptr_t)start;
+
+ LIST_FOREACH(dma, &sc->sc_dmalist, dma_list)
+ if (dma->dma_addr == start) {
+ pstart = dma->dma_map->dm_segs[0].ds_addr;
+ break;
+ }
+ if (pstart == 0) {
+ device_printf(sc->sc_dev, "bad addr %p\n", start);
+ return EINVAL;
+ }
+
+ ch->ch_intr = intr;
+ ch->ch_intrarg = intrarg;
+ ch->ch_start_phys = ch->ch_cur_phys = pstart;
+ ch->ch_end_phys = pstart + psize;
+ ch->ch_blksize = blksize;
+
+ /* Flush FIFO */
+ val = I2S_READ(sc, DA_FCTL);
+ I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FTX);
+ I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FTX);
+
+ /* Reset TX sample counter */
+ I2S_WRITE(sc, DA_TXCNT, 0);
+
+ /* Enable transmitter block */
+ val = I2S_READ(sc, DA_CTL);
+ I2S_WRITE(sc, DA_CTL, val | DA_CTL_TXEN);
+
+ /* Enable TX DRQ */
+ val = I2S_READ(sc, DA_INT);
+ I2S_WRITE(sc, DA_INT, val | DA_INT_TX_DRQ);
+
+ /* Start DMA transfer */
+ error = sunxi_i2s_transfer(ch);
+ if (error != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "failed to start DMA transfer: %d\n", error);
+ return error;
+ }
+
+ return 0;
+}
+
+static int
+sunxi_i2s_trigger_input(void *priv, void *start, void *end, int blksize,
+ void (*intr)(void *), void *intrarg, const audio_params_t *params)
+{
+ struct sunxi_i2s_softc * const sc = priv;
+ struct sunxi_i2s_chan *ch = &sc->sc_rchan;
+ struct sunxi_i2s_dma *dma;
+ bus_addr_t pstart;
+ bus_size_t psize;
+ uint32_t val;
+ int error;
+
+ pstart = 0;
+ psize = (uintptr_t)end - (uintptr_t)start;
+
+ LIST_FOREACH(dma, &sc->sc_dmalist, dma_list)
+ if (dma->dma_addr == start) {
+ pstart = dma->dma_map->dm_segs[0].ds_addr;
+ break;
+ }
+ if (pstart == 0) {
+ device_printf(sc->sc_dev, "bad addr %p\n", start);
+ return EINVAL;
+ }
+
+ ch->ch_intr = intr;
+ ch->ch_intrarg = intrarg;
+ ch->ch_start_phys = ch->ch_cur_phys = pstart;
+ ch->ch_end_phys = pstart + psize;
+ ch->ch_blksize = blksize;
+
+ /* Flush FIFO */
+ val = I2S_READ(sc, DA_FCTL);
+ I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FRX);
+ I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FRX);
+
+ /* Reset RX sample counter */
+ I2S_WRITE(sc, DA_RXCNT, 0);
+
+ /* Enable receiver block */
+ val = I2S_READ(sc, DA_CTL);
+ I2S_WRITE(sc, DA_CTL, val | DA_CTL_RXEN);
+
+ /* Enable RX DRQ */
+ val = I2S_READ(sc, DA_INT);
+ I2S_WRITE(sc, DA_INT, val | DA_INT_RX_DRQ);
+
+ /* Start DMA transfer */
+ error = sunxi_i2s_transfer(ch);
+ if (error != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "failed to start DMA transfer: %d\n", error);
+ return error;
+ }
+
+ return 0;
+}
+
+static int
+sunxi_i2s_halt_output(void *priv)
+{
+ struct sunxi_i2s_softc * const sc = priv;
+ struct sunxi_i2s_chan *ch = &sc->sc_pchan;
+ uint32_t val;
+
+ /* Disable DMA channel */
+ fdtbus_dma_halt(ch->ch_dma);
+
+ /* Disable transmitter block */
+ val = I2S_READ(sc, DA_CTL);
+ I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_TXEN);
+
+ /* Disable TX DRQ */
+ val = I2S_READ(sc, DA_INT);
+ I2S_WRITE(sc, DA_INT, val & ~DA_INT_TX_DRQ);
+
+ ch->ch_intr = NULL;
+ ch->ch_intrarg = NULL;
+
+ return 0;
+}
+
+static int
+sunxi_i2s_halt_input(void *priv)
+{
+ struct sunxi_i2s_softc * const sc = priv;
+ struct sunxi_i2s_chan *ch = &sc->sc_rchan;
+ uint32_t val;
+
+ /* Disable DMA channel */
+ fdtbus_dma_halt(ch->ch_dma);
+
+ /* Disable receiver block */
+ val = I2S_READ(sc, DA_CTL);
+ I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_RXEN);
+
+ /* Disable RX DRQ */
+ val = I2S_READ(sc, DA_INT);
+ I2S_WRITE(sc, DA_INT, val & ~DA_INT_RX_DRQ);
+
+ return 0;
+}
+
+static void
+sunxi_i2s_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread)
+{
+ struct sunxi_i2s_softc * const sc = priv;
+
+ *intr = &sc->sc_intr_lock;
+ *thread = &sc->sc_lock;
+}
+
+static const struct audio_hw_if sunxi_i2s_hw_if = {
+ .open = sunxi_i2s_open,
+ .close = sunxi_i2s_close,
+ .drain = NULL,
+ .query_encoding = sunxi_i2s_query_encoding,
+ .set_params = sunxi_i2s_set_params,
+ .allocm = sunxi_i2s_allocm,
+ .freem = sunxi_i2s_freem,
+ .mappage = sunxi_i2s_mappage,
+ .get_props = sunxi_i2s_get_props,
+ .round_blocksize = sunxi_i2s_round_blocksize,
+ .round_buffersize = sunxi_i2s_round_buffersize,
+ .trigger_output = sunxi_i2s_trigger_output,
+ .trigger_input = sunxi_i2s_trigger_input,
+ .halt_output = sunxi_i2s_halt_output,
+ .halt_input = sunxi_i2s_halt_input,
+ .get_locks = sunxi_i2s_get_locks,
+};
+
+static void
+sunxi_i2s_dmaintr(void *priv)
+{
+ struct sunxi_i2s_chan * const ch = priv;
+ struct sunxi_i2s_softc * const sc = ch->ch_sc;
+
+ mutex_enter(&sc->sc_intr_lock);
+ ch->ch_cur_phys += ch->ch_blksize;
+ if (ch->ch_cur_phys >= ch->ch_end_phys)
+ ch->ch_cur_phys = ch->ch_start_phys;
+
+ if (ch->ch_intr) {
+ ch->ch_intr(ch->ch_intrarg);
+ sunxi_i2s_transfer(ch);
+ }
+ mutex_exit(&sc->sc_intr_lock);
+}
+
+static int
+sunxi_i2s_chan_init(struct sunxi_i2s_softc *sc,
+ struct sunxi_i2s_chan *ch, u_int mode, const char *dmaname)
+{
+ ch->ch_sc = sc;
+ ch->ch_mode = mode;
+ ch->ch_dma = fdtbus_dma_get(sc->sc_phandle, dmaname, sunxi_i2s_dmaintr, ch);
+ if (ch->ch_dma == NULL) {
+ aprint_error(": couldn't get dma channel \"%s\"\n", dmaname);
+ return ENXIO;
+ }
+
+ if (mode == AUMODE_PLAY) {
+ ch->ch_req.dreq_dir = FDT_DMA_WRITE;
+ ch->ch_req.dreq_dev_phys =
+ sc->sc_baseaddr + DA_TXFIFO;
+ } else {
+ ch->ch_req.dreq_dir = FDT_DMA_READ;
+ ch->ch_req.dreq_dev_phys =
+ sc->sc_baseaddr + DA_RXFIFO;
+ }
+ ch->ch_req.dreq_mem_opt.opt_bus_width = 32;
+ ch->ch_req.dreq_mem_opt.opt_burst_len = 8;
+ ch->ch_req.dreq_dev_opt.opt_bus_width = 32;
+ ch->ch_req.dreq_dev_opt.opt_burst_len = 8;
+
+ return 0;
+}
+
+static int
+sunxi_i2s_dai_set_sysclk(audio_dai_tag_t dai, u_int rate, int dir)
+{
+ struct sunxi_i2s_softc * const sc = audio_dai_private(dai);
+ uint32_t val;
+
+ /* XXX */
+
+ val = DA_CLKD_MCLKO_EN;
+ val |= __SHIFTIN(DA_CLKD_BCLKDIV_16, DA_CLKD_BCLKDIV);
+ val |= __SHIFTIN(DA_CLKD_MCLKDIV_1, DA_CLKD_MCLKDIV);
+
+ I2S_WRITE(sc, DA_CLKD, val);
+
+ return 0;
+}
+
+static int
+sunxi_i2s_dai_set_format(audio_dai_tag_t dai, u_int format)
+{
+ struct sunxi_i2s_softc * const sc = audio_dai_private(dai);
+ uint32_t ctl, fat0;
+
+ const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK);
+ const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK);
+ const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK);
+
+ ctl = I2S_READ(sc, DA_CTL);
+ fat0 = I2S_READ(sc, DA_FAT0);
+
+ fat0 &= ~DA_FAT0_FMT;
+ switch (fmt) {
+ case AUDIO_DAI_FORMAT_I2S:
+ fat0 |= __SHIFTIN(DA_FMT_I2S, DA_FAT0_FMT);
+ break;
+ case AUDIO_DAI_FORMAT_RJ:
+ fat0 |= __SHIFTIN(DA_FMT_RJ, DA_FAT0_FMT);
+ break;
+ case AUDIO_DAI_FORMAT_LJ:
+ fat0 |= __SHIFTIN(DA_FMT_LJ, DA_FAT0_FMT);
+ break;
+ default:
+ return EINVAL;
+ }
+
+ fat0 &= ~(DA_FAT0_LRCP|DA_FAT0_BCP);
+ if (AUDIO_DAI_POLARITY_B(pol))
+ fat0 |= __SHIFTIN(DA_BCP_INVERTED, DA_FAT0_BCP);
+ if (AUDIO_DAI_POLARITY_F(pol))
+ fat0 |= __SHIFTIN(DA_LRCP_INVERTED, DA_FAT0_LRCP);
+
+ switch (clk) {
+ case AUDIO_DAI_CLOCK_CBM_CFM:
+ ctl |= DA_CTL_MS; /* codec is master */
+ break;
+ case AUDIO_DAI_CLOCK_CBS_CFS:
+ ctl &= ~DA_CTL_MS; /* codec is slave */
+ break;
+ default:
+ return EINVAL;
+ }
+
+ ctl &= ~DA_CTL_PCM;
+
+ I2S_WRITE(sc, DA_CTL, ctl);
+ I2S_WRITE(sc, DA_FAT0, fat0);
+
+ return 0;
+}
+
+static audio_dai_tag_t
+sunxi_i2s_dai_get_tag(device_t dev, const void *data, size_t len)
+{
+ struct sunxi_i2s_softc * const sc = device_private(dev);
+
+ if (len != 4)
+ return NULL;
+
+ return &sc->sc_dai;
+}
+
+static struct fdtbus_dai_controller_func sunxi_i2s_dai_funcs = {
+ .get_tag = sunxi_i2s_dai_get_tag
+};
+
+static int
+sunxi_i2s_clock_init(int phandle)
+{
+ struct fdtbus_reset *rst;
+ struct clk *clk;
+ int error;
+
+ /* Set module clock to 24.576MHz, suitable for 48 kHz sampling rates */
+ clk = fdtbus_clock_get(phandle, "mod");
+ if (clk == NULL) {
+ aprint_error(": couldn't find mod clock\n");
+ return ENXIO;
+ }
+ error = clk_set_rate(clk, SUNXI_I2S_CLK_RATE);
+ if (error != 0) {
+ aprint_error(": couldn't set mod clock rate: %d\n", error);
+ return error;
+ }
+ error = clk_enable(clk);
+ if (error != 0) {
+ aprint_error(": couldn't enable mod clock: %d\n", error);
+ return error;
+ }
+
+ /* Enable APB clock */
+ clk = fdtbus_clock_get(phandle, "apb");
+ if (clk == NULL) {
+ aprint_error(": couldn't find apb clock\n");
+ return ENXIO;
+ }
+ error = clk_enable(clk);
+ if (error != 0) {
+ aprint_error(": couldn't enable apb clock: %d\n", error);
+ return error;
+ }
+
+ /* De-assert reset */
+ rst = fdtbus_reset_get(phandle, "rst");
+ if (rst == NULL) {
+ aprint_error(": couldn't find reset\n");
+ return ENXIO;
+ }
+ error = fdtbus_reset_deassert(rst);
+ if (error != 0) {
+ aprint_error(": couldn't de-assert reset: %d\n", error);
+ return error;
+ }
+
+ return 0;
+}
+
+static int
+sunxi_i2s_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compat_data(faa->faa_phandle, compat_data);
+}
+
+static void
+sunxi_i2s_attach(device_t parent, device_t self, void *aux)
+{
+ struct sunxi_i2s_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ bus_addr_t addr;
+ bus_size_t size;
+ uint32_t val;
+ int error;
+
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+
+ if (sunxi_i2s_clock_init(phandle) != 0)
+ return;
+
+ sc->sc_dev = self;
+ sc->sc_phandle = phandle;
+ sc->sc_baseaddr = addr;
+ sc->sc_bst = faa->faa_bst;
+ if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
+ aprint_error(": couldn't map registers\n");
+ return;
+ }
+ sc->sc_dmat = faa->faa_dmat;
+ LIST_INIT(&sc->sc_dmalist);
+ sc->sc_cfg = (void *)of_search_compatible(phandle, compat_data)->data;
+ mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
+ mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED);
+
+ if (sunxi_i2s_chan_init(sc, &sc->sc_pchan, AUMODE_PLAY, "tx") != 0 ||
+ sunxi_i2s_chan_init(sc, &sc->sc_rchan, AUMODE_RECORD, "rx") != 0) {
+ aprint_error(": couldn't setup channels\n");
+ return;
+ }
+
+ aprint_naive("\n");
+ aprint_normal(": %s\n", sc->sc_cfg->name);
+
+ /* Reset */
+ val = I2S_READ(sc, DA_CTL);
+ val &= ~(DA_CTL_TXEN|DA_CTL_RXEN|DA_CTL_GEN);
+ I2S_WRITE(sc, DA_CTL, val);
+
+ val = I2S_READ(sc, DA_FCTL);
+ val &= ~(DA_FCTL_FTX|DA_FCTL_FRX);
+ I2S_WRITE(sc, DA_FCTL, val);
+
+ I2S_WRITE(sc, DA_TXCNT, 0);
+ I2S_WRITE(sc, DA_RXCNT, 0);
+
+ /* Enable */
+ I2S_WRITE(sc, DA_CTL, DA_CTL_GEN | DA_CTL_SDO_EN);
+
+ /* Setup channels */
+ I2S_WRITE(sc, sc->sc_cfg->txchmap, 0x76543210);
+ I2S_WRITE(sc, sc->sc_cfg->txchsel, __SHIFTIN(1, DA_CHSEL_SEL) |
+ __SHIFTIN(3, DA_CHSEL_EN));
+ I2S_WRITE(sc, sc->sc_cfg->rxchmap, 0x76543210);
+ I2S_WRITE(sc, sc->sc_cfg->rxchsel, __SHIFTIN(1, DA_CHSEL_SEL) |
+ __SHIFTIN(3, DA_CHSEL_EN));
+
+ sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD;
+ sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE;
+ sc->sc_format.validbits = 16;
+ sc->sc_format.precision = 16;
+ sc->sc_format.channels = 2;
+ sc->sc_format.channel_mask = AUFMT_STEREO;
+ sc->sc_format.frequency_type = 0;
+ sc->sc_format.frequency[0] = sc->sc_format.frequency[1] = 48000;
+
+ error = auconv_create_encodings(&sc->sc_format, 1, &sc->sc_encodings);
+ if (error) {
+ aprint_error_dev(self, "couldn't create encodings\n");
+ return;
+ }
+
+ sc->sc_dai.dai_set_sysclk = sunxi_i2s_dai_set_sysclk;
+ sc->sc_dai.dai_set_format = sunxi_i2s_dai_set_format;
+ sc->sc_dai.dai_hw_if = &sunxi_i2s_hw_if;
+ sc->sc_dai.dai_dev = self;
+ sc->sc_dai.dai_priv = sc;
+ fdtbus_register_dai_controller(self, phandle, &sunxi_i2s_dai_funcs);
+}
+
+CFATTACH_DECL_NEW(sunxi_i2s, sizeof(struct sunxi_i2s_softc),
+ sunxi_i2s_match, sunxi_i2s_attach, NULL, NULL);
