Module Name: src Committed By: ryo Date: Thu May 17 08:24:29 UTC 2018
Modified Files: src/sys/arch/aarch64/aarch64: locore.S Log Message: allow to execute cache operation (DC CVAU,DC CIVAC, DC CVAC, IC IVAU) from userland. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/aarch64/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/aarch64/aarch64/locore.S diff -u src/sys/arch/aarch64/aarch64/locore.S:1.5 src/sys/arch/aarch64/aarch64/locore.S:1.6 --- src/sys/arch/aarch64/aarch64/locore.S:1.5 Sun Apr 1 04:35:03 2018 +++ src/sys/arch/aarch64/aarch64/locore.S Thu May 17 08:24:28 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.5 2018/04/01 04:35:03 ryo Exp $ */ +/* $NetBSD: locore.S,v 1.6 2018/05/17 08:24:28 ryo Exp $ */ /* * Copyright (c) 2017 Ryo Shimizu <r...@nerv.org> @@ -36,7 +36,7 @@ #include <aarch64/pte.h> #include "assym.h" -RCSID("$NetBSD: locore.S,v 1.5 2018/04/01 04:35:03 ryo Exp $") +RCSID("$NetBSD: locore.S,v 1.6 2018/05/17 08:24:28 ryo Exp $") /* #define DEBUG_LOCORE */ /* #define DEBUG_MMU */ @@ -692,6 +692,7 @@ sctlr_set: .quad ( \ SCTLR_LSMAOE | /* Load/Store Multiple Atomicity and Ordering */ \ SCTLR_nTLSMD | /* no Trap Load/Store Multiple to Device */ \ + SCTLR_UCI | /* Enables EL0 DC {CVAU,CIVAC,CVAC}, IC IVAU */ \ SCTLR_SPAN | /* This field resets to 1 */ \ SCTLR_UCT | /* Enables EL0 access to the CTR_EL0 */ \ SCTLR_DZE | /* Enables access to the DC ZVA instruction */ \ @@ -705,7 +706,6 @@ sctlr_set: 0) sctlr_clear: .quad ( \ - SCTLR_UCI | /* Enable EL0 DC {CVAU,CIVAC,CVAC}, IC IVAU */ \ SCTLR_IESB | /* Enable Implicit ErrorSynchronizationBarrier */ \ SCTLR_WXN | /* Write permission implies Execute Never (W^X) */ \ SCTLR_nTWE | /* EL0 WFE non-trapping */ \