Module Name: src Committed By: thorpej Date: Sun May 20 15:15:41 UTC 2018
Added Files: src/share/man/man4: gpiopps.4 src/sys/modules/gpiopps: Makefile gpiopps.ioconf Log Message: Add a 1PPS-over-GPIO driver, originally by Brad Spencer, with changes by me to adapt to the new GPIO interrupt interface and support a wider variety of GPIO pin configuations. PR kern/51676 (Oops, forgot to "cvs add" these items previously.) To generate a diff of this commit: cvs rdiff -u -r0 -r1.1 src/share/man/man4/gpiopps.4 cvs rdiff -u -r0 -r1.1 src/sys/modules/gpiopps/Makefile \ src/sys/modules/gpiopps/gpiopps.ioconf Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Added files: Index: src/share/man/man4/gpiopps.4 diff -u /dev/null src/share/man/man4/gpiopps.4:1.1 --- /dev/null Sun May 20 15:15:41 2018 +++ src/share/man/man4/gpiopps.4 Sun May 20 15:15:40 2018 @@ -0,0 +1,106 @@ +.\" $NetBSD: gpiopps.4,v 1.1 2018/05/20 15:15:40 thorpej Exp $ +.\" +.\" Copyright (c) 2016 Brad Spencer <b...@anduin.eldar.org> +.\" +.\" Permission to use, copy, modify, and distribute this software for any +.\" purpose with or without fee is hereby granted, provided that the above +.\" copyright notice and this permission notice appear in all copies. +.\" +.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +.\" +.Dd May 11, 2018 +.Dt GPIOPPS 4 +.Os +.Sh NAME +.Nm gpiopps +.Nd install a PPS handler on GPIO pins +.Sh SYNOPSIS +.Cd "gpiopps* at gpio? offset 0 mask 0x1 flag 0x0" +.Sh DESCRIPTION +The +.Nm +driver provides a 1PPS handler using the PPSAPI on one or two GPIO pins. +.Pp +The base pin number is specified in the kernel configuration file with the +.Ar offset +locator. +The +.Ar mask +should have 1 or 2 bits set, indicating which pins offset from the +base pin should be used +.Pq 0 .. 31 . +Pin configurations are discussed below. +.Pp +The +.Ar flag +locator modifies the pin configuraiton: +.Bl -tag -width "XXXXXXXX" +.It Dv 0x01 +The PPS ASSERT signal should be triggered on the negative +.Pq falling +edge of the +assert pin. +The default is to trigger on the positive +.Pq rising +edge of the pin. +.It Dv 0x02 +By default, +.Nm +will use double-edge triggering when only a single pin is specified +and the underlying GPIO hardware supports it. +This flag disables the use of double-edge triggering. +.El +.Pp +If a single pin is specified, +.Nm +uses double-edge triggering to support ASSERT and CLEAR PPS signals. +If the underlying GPIO hardware does not support double-edge triggering, +or if this feature is diabled in the +.Ar flag +locator, then only ASSERT will be signaled on the specified edge. +.Pp +If two pins are specified, the first pin is used to trigger the +ASSERT signal and the second pin is used to trigger the CLEAR +signal. +The ASSERT pin's trigger edge is specified by by the +.Ar flag +locator, and the CLEAR pin triggers on the opposite edge. +This allows ASSERT and CLEAR signals to be triggered even if the underlying +GPIO hardware does not support double-edge triggering. +In this scenario, both GPIO pins would be connected in parallel to the +device sending the 1PPS signals. +.Pp +The +.Ar offset , +.Ar mask , +and +.Ar flag +locators can also be specified when +.Nm +is attached at runtime using the +.Dv GPIOATTACH +.Xr ioctl 2 +on the +.Xr gpio 4 +device. +.Sh SEE ALSO +.Xr gpio 4 , +.Xr drvctl 8 , +.Xr gpioctl 8 +.Sh HISTORY +The +.Nm +driver first appeared in +.Nx 9.0 . +.Sh AUTHORS +.An -nosplit +The +.Nm +driver was written by +.An Brad Spencer Aq Mt b...@anduin.eldar.org Index: src/sys/modules/gpiopps/Makefile diff -u /dev/null src/sys/modules/gpiopps/Makefile:1.1 --- /dev/null Sun May 20 15:15:41 2018 +++ src/sys/modules/gpiopps/Makefile Sun May 20 15:15:41 2018 @@ -0,0 +1,13 @@ +# $NetBSD: Makefile,v 1.1 2018/05/20 15:15:41 thorpej Exp $ + +.include "../Makefile.inc" + +.PATH: ${S}/dev/gpio + +KMOD= gpiopps +IOCONF= gpiopps.ioconf +SRCS= gpiopps.c + +CPPFLAGS+= -I${S}/gpio + +.include <bsd.kmodule.mk> Index: src/sys/modules/gpiopps/gpiopps.ioconf diff -u /dev/null src/sys/modules/gpiopps/gpiopps.ioconf:1.1 --- /dev/null Sun May 20 15:15:41 2018 +++ src/sys/modules/gpiopps/gpiopps.ioconf Sun May 20 15:15:41 2018 @@ -0,0 +1,8 @@ +# $NetBSD: gpiopps.ioconf,v 1.1 2018/05/20 15:15:41 thorpej Exp $ + +ioconf gpiopps + +include "conf/files" + +pseudo-root gpio* +gpiopps* at gpio? offset ? mask ? flag ?