Module Name: src
Committed By: msaitoh
Date: Thu May 31 03:29:01 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Fix the bit location of SSBD in the macro for snprintb.
To generate a diff of this commit:
cvs rdiff -u -r1.125 -r1.126 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.125 src/sys/arch/x86/include/specialreg.h:1.126
--- src/sys/arch/x86/include/specialreg.h:1.125 Wed May 23 07:24:37 2018
+++ src/sys/arch/x86/include/specialreg.h Thu May 31 03:29:01 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.125 2018/05/23 07:24:37 maxv Exp $ */
+/* $NetBSD: specialreg.h,v 1.126 2018/05/31 03:29:01 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -405,9 +405,10 @@
#define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */
#define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */
-#define CPUID_SEF_FLAGS2 \
- "\20" "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
- "\33" "IBRS" "\34" "STIBP" "\36" "ARCH_CAP" "\38" "SSBD"
+#define CPUID_SEF_FLAGS2 "\20" \
+ "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
+ "\33" "IBRS" "\34" "STIBP" \
+ "\36" "ARCH_CAP" "\40" "SSBD"
/*
* CPUID Processor extended state Enumeration Fn0000000d
