Module Name: src
Committed By: msaitoh
Date: Thu Jun 14 07:19:47 UTC 2018
Modified Files:
src/sys/dev/pci: if_skreg.h
Log Message:
s/regisrer/register/. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/dev/pci/if_skreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/if_skreg.h
diff -u src/sys/dev/pci/if_skreg.h:1.20 src/sys/dev/pci/if_skreg.h:1.21
--- src/sys/dev/pci/if_skreg.h:1.20 Thu Jun 14 06:58:15 2018
+++ src/sys/dev/pci/if_skreg.h Thu Jun 14 07:19:47 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: if_skreg.h,v 1.20 2018/06/14 06:58:15 msaitoh Exp $ */
+/* $NetBSD: if_skreg.h,v 1.21 2018/06/14 07:19:47 msaitoh Exp $ */
/*-
* Copyright (c) 2003 The NetBSD Foundation, Inc.
@@ -1079,7 +1079,7 @@
#define SK_RBCTL_STORENFWD_OFF 0x10
#define SK_RBCTL_STORENFWD_ON 0x20
-/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */
+/* Block 24 -- RX MAC FIFO 1 registers and LINK_SYNC counter */
#define SK_RXF1_END 0x0C00
#define SK_RXF1_WPTR 0x0C04
#define SK_RXF1_RPTR 0x0C0C
@@ -1128,7 +1128,7 @@
#define SK_RFCTL_FIFO_THRESHOLD 0x0a /* flush threshold (default) */
-/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */
+/* Block 25 -- RX MAC FIFO 2 registers and LINK_SYNC counter */
#define SK_RXF2_END 0x0C80
#define SK_RXF2_WPTR 0x0C84
#define SK_RXF2_RPTR 0x0C8C
@@ -1174,7 +1174,7 @@
#define SK_LINKLED_BLINK_OFF 0x0010
#define SK_LINKLED_BLINK_ON 0x0020
-/* Block 26 -- TX MAC FIFO 1 regisrers */
+/* Block 26 -- TX MAC FIFO 1 registers */
#define SK_TXF1_END 0x0D00
#define SK_TXF1_WPTR 0x0D04
#define SK_TXF1_RPTR 0x0D0C
@@ -1213,7 +1213,7 @@
#define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */
#define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */
-/* Block 27 -- TX MAC FIFO 2 regisrers */
+/* Block 27 -- TX MAC FIFO 2 registers */
#define SK_TXF2_END 0x0D80
#define SK_TXF2_WPTR 0x0D84
#define SK_TXF2_RPTR 0x0D8C
