Module Name: src
Committed By: jmcneill
Date: Tue Jul 3 09:39:32 UTC 2018
Modified Files:
src/sys/arch/arm/samsung: exynos5422_clock.c
Log Message:
Add USB clocks and missing MMC biu clocks
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/samsung/exynos5422_clock.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/samsung/exynos5422_clock.c
diff -u src/sys/arch/arm/samsung/exynos5422_clock.c:1.7 src/sys/arch/arm/samsung/exynos5422_clock.c:1.8
--- src/sys/arch/arm/samsung/exynos5422_clock.c:1.7 Mon Jul 2 20:24:55 2018
+++ src/sys/arch/arm/samsung/exynos5422_clock.c Tue Jul 3 09:39:32 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos5422_clock.c,v 1.7 2018/07/02 20:24:55 jmcneill Exp $ */
+/* $NetBSD: exynos5422_clock.c,v 1.8 2018/07/03 09:39:32 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: exynos5422_clock.c,v 1.7 2018/07/02 20:24:55 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: exynos5422_clock.c,v 1.8 2018/07/03 09:39:32 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -374,14 +374,17 @@ static const struct clk_funcs exynos5422
#define EXYNOS5422_SRC_PERIC1 0x10254
#define EXYNOS5422_SRC_ISP 0x10270
#define EXYNOS5422_SRC_TOP10 0x10280
-#define EXYNOS5422_SRC_TOP11 0x10280
-#define EXYNOS5422_SRC_TOP12 0x10280
+#define EXYNOS5422_SRC_TOP11 0x10284
+#define EXYNOS5422_SRC_TOP12 0x10288
+#define EXYNOS5422_DIV_TOP0 0x10500
#define EXYNOS5422_DIV_FSYS1 0x1054c
#define EXYNOS5422_DIV_PERIC0 0x10558
+#define EXYNOS5422_GATE_BUS_FSYS0 0x10740
#define EXYNOS5422_GATE_TOP_SCLK_FSYS 0x10840
#define EXYNOS5422_GATE_TOP_SCLK_PERIC 0x10850
+#define EXYNOS5422_GATE_IP_FSYS 0x10944
static const char *mout_cpll_p[] = { "fin_pll", "fout_cpll" };
static const char *mout_dpll_p[] = { "fin_pll", "fout_dpll" };
@@ -390,9 +393,19 @@ static const char *mout_spll_p[] = { "fi
static const char *mout_ipll_p[] = { "fin_pll", "fout_ipll" };
static const char *mout_epll_p[] = { "fin_pll", "fout_epll" };
static const char *mout_rpll_p[] = { "fin_pll", "fout_rpll" };
+static const char *mout_group1_p[] =
+ { "sclk_cpll", "sclk_dpll", "sclk_mpp" };
static const char *mout_group2_p[] =
{ "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll",
"sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
+static const char *mout_user_aclk200_fsys_p[] =
+ { "fin_pll", "mout_sw_aclk200_fsys" };
+static const char *mout_user_aclk200_fsys2_p[] =
+ { "fin_pll", "mout_sw_aclk200_fsys2" };
+static const char *mout_sw_aclk200_fsys_p[] =
+ { "dout_aclk200_fsys", "sclk_spll" };
+static const char *mout_sw_aclk200_fsys2_p[] =
+ { "dout_aclk200_fsys2", "sclk_spll" };
static struct exynos_clk exynos5422_clocks[] = {
CLK_FIXED("fin_pll", EXYNOS_F_IN_FREQ),
@@ -435,6 +448,19 @@ static struct exynos_clk exynos5422_cloc
CLK_MUXF("sclk_rpll", "mout_rpll", EXYNOS5422_SRC_TOP6, __BIT(16),
CLK_SET_RATE_PARENT, mout_rpll_p),
+ CLK_MUX("mout_sw_aclk200_fsys", EXYNOS5422_SRC_TOP10, __BIT(24),
+ mout_sw_aclk200_fsys_p),
+ CLK_MUX("mout_sw_aclk200_fsys2", EXYNOS5422_SRC_TOP10, __BIT(12),
+ mout_sw_aclk200_fsys2_p),
+ CLK_MUX("mout_user_aclk200_fsys", EXYNOS5422_SRC_TOP3, __BIT(28),
+ mout_user_aclk200_fsys_p),
+ CLK_MUX("mout_user_aclk200_fsys2", EXYNOS5422_SRC_TOP3, __BIT(12),
+ mout_user_aclk200_fsys2_p),
+ CLK_MUX("mout_aclk200_fsys", EXYNOS5422_SRC_TOP0, __BITS(25,24),
+ mout_group1_p),
+ CLK_MUX("mout_aclk200_fsys2", EXYNOS5422_SRC_TOP0, __BITS(13,12),
+ mout_group1_p),
+
CLK_MUX("mout_mmc0", EXYNOS5422_SRC_FSYS, __BITS(10,8),
mout_group2_p),
CLK_MUX("mout_mmc1", EXYNOS5422_SRC_FSYS, __BITS(14,12),
@@ -450,6 +476,9 @@ static struct exynos_clk exynos5422_cloc
CLK_MUX("mout_uart3", EXYNOS5422_SRC_PERIC0, __BITS(18,16),
mout_group2_p),
+ CLK_DIV("dout_aclk200_fsys", "mout_aclk200_fsys", EXYNOS5422_DIV_TOP0, __BITS(30,28)),
+ CLK_DIV("dout_aclk200_fsys2", "mout_aclk200_fsys2", EXYNOS5422_DIV_TOP0, __BITS(14,12)),
+
CLK_DIV("dout_mmc0", "mout_mmc0", EXYNOS5422_DIV_FSYS1, __BITS(9,0)),
CLK_DIV("dout_mmc1", "mout_mmc1", EXYNOS5422_DIV_FSYS1, __BITS(19,10)),
CLK_DIV("dout_mmc2", "mout_mmc2", EXYNOS5422_DIV_FSYS1, __BITS(29,20)),
@@ -462,6 +491,11 @@ static struct exynos_clk exynos5422_cloc
CLK_DIV("dout_uart3", "mout_uart3", EXYNOS5422_DIV_PERIC0,
__BITS(23,20)),
+ CLK_GATE("aclk200_fsys", "mout_user_aclk200_fsys", EXYNOS5422_GATE_BUS_FSYS0,
+ __BIT(9), CLK_SET_RATE_PARENT),
+ CLK_GATE("aclk200_fsys2", "mout_user_aclk200_fsys2", EXYNOS5422_GATE_BUS_FSYS0,
+ __BIT(10), CLK_SET_RATE_PARENT),
+
CLK_GATE("sclk_mmc0", "dout_mmc0", EXYNOS5422_GATE_TOP_SCLK_FSYS,
__BIT(0), CLK_SET_RATE_PARENT),
CLK_GATE("sclk_mmc1", "dout_mmc1", EXYNOS5422_GATE_TOP_SCLK_FSYS,
@@ -476,6 +510,19 @@ static struct exynos_clk exynos5422_cloc
__BIT(2), CLK_SET_RATE_PARENT),
CLK_GATE("sclk_uart3", "dout_uart3", EXYNOS5422_GATE_TOP_SCLK_PERIC,
__BIT(3), CLK_SET_RATE_PARENT),
+
+ CLK_GATE("mmc0", "aclk200_fsys2", EXYNOS5422_GATE_IP_FSYS,
+ __BIT(12), CLK_SET_RATE_PARENT),
+ CLK_GATE("mmc1", "aclk200_fsys2", EXYNOS5422_GATE_IP_FSYS,
+ __BIT(13), CLK_SET_RATE_PARENT),
+ CLK_GATE("mmc2", "aclk200_fsys2", EXYNOS5422_GATE_IP_FSYS,
+ __BIT(14), CLK_SET_RATE_PARENT),
+ CLK_GATE("usbh20", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS,
+ __BIT(18), CLK_SET_RATE_PARENT),
+ CLK_GATE("usbd300", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS,
+ __BIT(19), CLK_SET_RATE_PARENT),
+ CLK_GATE("usbd301", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS,
+ __BIT(20), CLK_SET_RATE_PARENT),
};
static int exynos5422_clock_match(device_t, cfdata_t, void *);
