Module Name: src
Committed By: msaitoh
Date: Fri Jul 6 01:58:12 UTC 2018
Modified Files:
src/sys/dev/mii: mdio.h
Log Message:
Add PMA/PDM control 2 register bit definitions.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/dev/mii/mdio.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/mii/mdio.h
diff -u src/sys/dev/mii/mdio.h:1.8 src/sys/dev/mii/mdio.h:1.9
--- src/sys/dev/mii/mdio.h:1.8 Thu Jun 28 09:12:21 2018
+++ src/sys/dev/mii/mdio.h Fri Jul 6 01:58:12 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: mdio.h,v 1.8 2018/06/28 09:12:21 msaitoh Exp $ */
+/* $NetBSD: mdio.h,v 1.9 2018/07/06 01:58:12 msaitoh Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -91,7 +91,57 @@
#define MDIO_PMAPMD_SPEED 4 /* PMA/PMD speed ability */
#define MDIO_PMAPMD_DEVS1 5 /* PMA/PMD devices in package 1 */
#define MDIO_PMAPMD_DEVS2 6 /* PMA/PMD devices in package 2 */
+
#define MDIO_PMAPMD_CTRL2 7 /* PMA/PMD control 2 */
+#define PMAPMD_CTRL2_PIASE 0x0200
+#define PMAPMD_CTRL2_PEASE 0x0100
+#define PMAPMD_CTRL2_TYPE_MASK 0x003f
+#define PMAPMD_CTRL2_TYPE_100G_SR4 0x2f
+#define PMAPMD_CTRL2_TYPE_100G_CR4 0x2e
+#define PMAPMD_CTRL2_TYPE_100G_KR4 0x2d
+#define PMAPMD_CTRL2_TYPE_100G_KP4 0x2c
+#define PMAPMD_CTRL2_TYPE_100G_ER4 0x2b
+#define PMAPMD_CTRL2_TYPE_100G_LR4 0x2a
+#define PMAPMD_CTRL2_TYPE_100G_SR10 0x29
+#define PMAPMD_CTRL2_TYPE_100G_CR10 0x28
+#define PMAPMD_CTRL2_TYPE_40G_ER4 0x25
+#define PMAPMD_CTRL2_TYPE_40G_FR 0x24
+#define PMAPMD_CTRL2_TYPE_40G_LR 0x23
+#define PMAPMD_CTRL2_TYPE_40G_SR4 0x22
+#define PMAPMD_CTRL2_TYPE_40G_CR4 0x21
+#define PMAPMD_CTRL2_TYPE_40G_KR4 0x20
+#define PMAPMD_CTRL2_TYPE_10_1G_PRX_U4 0x1f
+#define PMAPMD_CTRL2_TYPE_10G_PR_U4 0x1e
+#define PMAPMD_CTRL2_TYPE_10_1G_PRX_D4 0x1d
+#define PMAPMD_CTRL2_TYPE_10G_PR_D4 0x1c
+#define PMAPMD_CTRL2_TYPE_10G_PR_U3 0x1a
+#define PMAPMD_CTRL2_TYPE_10G_PR_U1 0x19
+#define PMAPMD_CTRL2_TYPE_10_1G_PRX_U3 0x18
+#define PMAPMD_CTRL2_TYPE_10_1G_PRX_U2 0x17
+#define PMAPMD_CTRL2_TYPE_10_1G_PRX_U1 0x16
+#define PMAPMD_CTRL2_TYPE_10G_PR_D3 0x15
+#define PMAPMD_CTRL2_TYPE_10G_PR_D2 0x14
+#define PMAPMD_CTRL2_TYPE_10G_PR_D1 0x13
+#define PMAPMD_CTRL2_TYPE_10_1G_PRX_D3 0x12
+#define PMAPMD_CTRL2_TYPE_10_1G_PRX_D2 0x11
+#define PMAPMD_CTRL2_TYPE_10_1G_PRX_D1 0x10
+#define PMAPMD_CTRL2_TYPE_10_T 0x0f
+#define PMAPMD_CTRL2_TYPE_100_TX 0x0e
+#define PMAPMD_CTRL2_TYPE_1000_KX 0x0d
+#define PMAPMD_CTRL2_TYPE_1000_T 0x0c
+#define PMAPMD_CTRL2_TYPE_10G_KR 0x0b
+#define PMAPMD_CTRL2_TYPE_10G_KX4 0x0a
+#define PMAPMD_CTRL2_TYPE_10G_T 0x09
+#define PMAPMD_CTRL2_TYPE_10G_LRM 0x08
+#define PMAPMD_CTRL2_TYPE_10G_SR 0x07
+#define PMAPMD_CTRL2_TYPE_10G_LR 0x06
+#define PMAPMD_CTRL2_TYPE_10G_ER 0x05
+#define PMAPMD_CTRL2_TYPE_10G_LX4 0x04
+#define PMAPMD_CTRL2_TYPE_10G_SW 0x03
+#define PMAPMD_CTRL2_TYPE_10G_LW 0x02
+#define PMAPMD_CTRL2_TYPE_10G_EW 0x01
+#define PMAPMD_CTRL2_TYPE_10G_CX4 0x00
+
#define MDIO_PMAPMD_10GSTAT2 8 /* 10G PMA/PMD status 2 */
#define MDIO_PMAPMD_10GTXDIS 9 /* 10G PMA/PMD transmit disable */
#define MDIO_PMAPMD_RXSIGDTCT 10 /* 10G PMD receive signal detect */
