Module Name: src
Committed By: maxv
Date: Fri Jul 13 09:37:32 UTC 2018
Modified Files:
src/share/man/man4: options.4
src/share/man/man9: intro.9
src/sys/arch/amd64/conf: ALL GENERIC files.amd64
src/sys/arch/i386/conf: ALL GENERIC NET4501 files.i386
src/sys/arch/x86/conf: files.x86
src/sys/arch/x86/include: specialreg.h sysarch.h
src/sys/arch/x86/x86: sys_machdep.c x86_machdep.c
src/sys/arch/xen/conf: files.compat
Removed Files:
src/sys/arch/x86/x86: pmc.c
Log Message:
Remove the X86PMC code I had written, replaced by tprof. Many defines
become unused in specialreg.h, so remove them. We don't want to add
defines all the time, there are countless PMCs on many generations, and
it's better to just inline the event/unit values.
To generate a diff of this commit:
cvs rdiff -u -r1.489 -r1.490 src/share/man/man4/options.4
cvs rdiff -u -r1.21 -r1.22 src/share/man/man9/intro.9
cvs rdiff -u -r1.93 -r1.94 src/sys/arch/amd64/conf/ALL
cvs rdiff -u -r1.495 -r1.496 src/sys/arch/amd64/conf/GENERIC
cvs rdiff -u -r1.104 -r1.105 src/sys/arch/amd64/conf/files.amd64
cvs rdiff -u -r1.442 -r1.443 src/sys/arch/i386/conf/ALL
cvs rdiff -u -r1.1182 -r1.1183 src/sys/arch/i386/conf/GENERIC
cvs rdiff -u -r1.100 -r1.101 src/sys/arch/i386/conf/NET4501
cvs rdiff -u -r1.394 -r1.395 src/sys/arch/i386/conf/files.i386
cvs rdiff -u -r1.101 -r1.102 src/sys/arch/x86/conf/files.x86
cvs rdiff -u -r1.127 -r1.128 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/x86/include/sysarch.h
cvs rdiff -u -r1.12 -r0 src/sys/arch/x86/x86/pmc.c
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/x86/x86/sys_machdep.c
cvs rdiff -u -r1.118 -r1.119 src/sys/arch/x86/x86/x86_machdep.c
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/xen/conf/files.compat
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/share/man/man4/options.4
diff -u src/share/man/man4/options.4:1.489 src/share/man/man4/options.4:1.490
--- src/share/man/man4/options.4:1.489 Thu Jul 12 10:46:41 2018
+++ src/share/man/man4/options.4 Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-.\" $NetBSD: options.4,v 1.489 2018/07/12 10:46:41 maxv Exp $
+.\" $NetBSD: options.4,v 1.490 2018/07/13 09:37:32 maxv Exp $
.\"
.\" Copyright (c) 1996
.\" Perry E. Metzger. All rights reserved.
@@ -30,7 +30,7 @@
.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\"
-.Dd July 12, 2018
+.Dd July 13, 2018
.Dt OPTIONS 4
.Os
.Sh NAME
@@ -2702,7 +2702,6 @@ bolded
.Xr gcc 1 ,
.Xr gdb 1 ,
.Xr ktrace 1 ,
-.Xr pmc 1 ,
.Xr quota 1 ,
.Xr vndcompress 1 ,
.Xr gettimeofday 2 ,
Index: src/share/man/man9/intro.9
diff -u src/share/man/man9/intro.9:1.21 src/share/man/man9/intro.9:1.22
--- src/share/man/man9/intro.9:1.21 Mon May 28 08:36:36 2018
+++ src/share/man/man9/intro.9 Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-.\" $NetBSD: intro.9,v 1.21 2018/05/28 08:36:36 wiz Exp $
+.\" $NetBSD: intro.9,v 1.22 2018/07/13 09:37:32 maxv Exp $
.\"
.\" Copyright (c) 1997, 2007 The NetBSD Foundation, Inc.
.\" All rights reserved.
@@ -27,7 +27,7 @@
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
.\" POSSIBILITY OF SUCH DAMAGE.
.\"
-.Dd May 30, 2017
+.Dd July 13, 2018
.Dt INTRO 9
.Os
.Sh NAME
@@ -628,10 +628,6 @@ Performs pattern matching on strings.
See
.Xr pmatch 9 .
.Pp
-Hardware Performance Monitoring Interface.
-See
-.Xr pmc 9 .
-.Pp
Add or remove a shutdown hook.
See
.Xr pmf 9 .
Index: src/sys/arch/amd64/conf/ALL
diff -u src/sys/arch/amd64/conf/ALL:1.93 src/sys/arch/amd64/conf/ALL:1.94
--- src/sys/arch/amd64/conf/ALL:1.93 Thu Jul 12 10:39:06 2018
+++ src/sys/arch/amd64/conf/ALL Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-# $NetBSD: ALL,v 1.93 2018/07/12 10:39:06 maya Exp $
+# $NetBSD: ALL,v 1.94 2018/07/13 09:37:32 maxv Exp $
# From NetBSD: GENERIC,v 1.787 2006/10/01 18:37:54 bouyer Exp
#
# ALL machine description file
@@ -17,7 +17,7 @@ include "arch/amd64/conf/std.amd64"
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "ALL-$Revision: 1.93 $"
+#ident "ALL-$Revision: 1.94 $"
maxusers 64 # estimated number of users
@@ -40,8 +40,6 @@ powernow0 at cpu0 # AMD PowerNow! and C
viac7temp* at cpu? # VIA C7 temperature sensor
vmt0 at cpu0 # VMware Tools
-options PMC # performance-monitoring counters support
-
# Beep when it is safe to power down the system (requires sysbeep)
options BEEP_ONHALT
# Some tunable details of the above feature (default values used below)
Index: src/sys/arch/amd64/conf/GENERIC
diff -u src/sys/arch/amd64/conf/GENERIC:1.495 src/sys/arch/amd64/conf/GENERIC:1.496
--- src/sys/arch/amd64/conf/GENERIC:1.495 Thu Jul 12 10:39:06 2018
+++ src/sys/arch/amd64/conf/GENERIC Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.495 2018/07/12 10:39:06 maya Exp $
+# $NetBSD: GENERIC,v 1.496 2018/07/13 09:37:32 maxv Exp $
#
# GENERIC machine description file
#
@@ -22,7 +22,7 @@ include "arch/amd64/conf/std.amd64"
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "GENERIC-$Revision: 1.495 $"
+#ident "GENERIC-$Revision: 1.496 $"
maxusers 64 # estimated number of users
@@ -88,8 +88,6 @@ est0 at cpu0 # Intel Enhanced SpeedSte
powernow0 at cpu0 # AMD PowerNow! and Cool'n'Quiet (non-ACPI)
vmt0 at cpu0 # VMware Tools
-options PMC # performance-monitoring counters support
-
# Alternate buffer queue strategies for better responsiveness under high
# disk I/O load.
#options BUFQ_READPRIO
Index: src/sys/arch/amd64/conf/files.amd64
diff -u src/sys/arch/amd64/conf/files.amd64:1.104 src/sys/arch/amd64/conf/files.amd64:1.105
--- src/sys/arch/amd64/conf/files.amd64:1.104 Wed May 23 07:45:35 2018
+++ src/sys/arch/amd64/conf/files.amd64 Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-# $NetBSD: files.amd64,v 1.104 2018/05/23 07:45:35 maxv Exp $
+# $NetBSD: files.amd64,v 1.105 2018/07/13 09:37:32 maxv Exp $
#
# new style config file for amd64 architecture
#
@@ -27,7 +27,6 @@ defflag opt_spectre.h SPECTRE_V2_GCC_MIT
# with the i386 (they include the opt_*.h for these)
#
-defflag PMC
defflag USER_LDT
defflag KASLR
defflag eisa.h EISA
Index: src/sys/arch/i386/conf/ALL
diff -u src/sys/arch/i386/conf/ALL:1.442 src/sys/arch/i386/conf/ALL:1.443
--- src/sys/arch/i386/conf/ALL:1.442 Tue Jul 10 19:58:13 2018
+++ src/sys/arch/i386/conf/ALL Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-# $NetBSD: ALL,v 1.442 2018/07/10 19:58:13 maya Exp $
+# $NetBSD: ALL,v 1.443 2018/07/13 09:37:32 maxv Exp $
# From NetBSD: GENERIC,v 1.787 2006/10/01 18:37:54 bouyer Exp
#
# ALL machine description file
@@ -17,7 +17,7 @@ include "arch/i386/conf/std.i386"
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "ALL-$Revision: 1.442 $"
+#ident "ALL-$Revision: 1.443 $"
maxusers 64 # estimated number of users
@@ -41,7 +41,6 @@ viac7temp* at cpu? # VIA C7 temperature
vmt0 at cpu0 # VMware Tools
options MTRR # memory-type range register syscall support
-options PMC # performance-monitoring counters support
options MULTIBOOT # Multiboot support (see multiboot(8))
Index: src/sys/arch/i386/conf/GENERIC
diff -u src/sys/arch/i386/conf/GENERIC:1.1182 src/sys/arch/i386/conf/GENERIC:1.1183
--- src/sys/arch/i386/conf/GENERIC:1.1182 Tue Jul 10 19:58:13 2018
+++ src/sys/arch/i386/conf/GENERIC Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.1182 2018/07/10 19:58:13 maya Exp $
+# $NetBSD: GENERIC,v 1.1183 2018/07/13 09:37:32 maxv Exp $
#
# GENERIC machine description file
#
@@ -22,7 +22,7 @@ include "arch/i386/conf/std.i386"
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "GENERIC-$Revision: 1.1182 $"
+#ident "GENERIC-$Revision: 1.1183 $"
maxusers 64 # estimated number of users
@@ -44,7 +44,6 @@ viac7temp* at cpu? # VIA C7 temperature
vmt0 at cpu0 # VMware Tools
options MTRR # memory-type range register syscall support
-options PMC # performance-monitoring counters support
options MULTIBOOT # Multiboot support (see multiboot(8))
Index: src/sys/arch/i386/conf/NET4501
diff -u src/sys/arch/i386/conf/NET4501:1.100 src/sys/arch/i386/conf/NET4501:1.101
--- src/sys/arch/i386/conf/NET4501:1.100 Mon Nov 6 02:57:18 2017
+++ src/sys/arch/i386/conf/NET4501 Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-# $NetBSD: NET4501,v 1.100 2017/11/06 02:57:18 rin Exp $
+# $NetBSD: NET4501,v 1.101 2018/07/13 09:37:32 maxv Exp $
#
# NET4501 -- kernel configuration for a Soekris Engineering net4501
# single-board computer.
@@ -10,7 +10,7 @@ include "arch/i386/conf/std.i386"
#options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "NET4501-$Revision: 1.100 $"
+#ident "NET4501-$Revision: 1.101 $"
maxusers 32 # estimated number of users
@@ -23,7 +23,6 @@ makeoptions COPTS="-Os"
#options USER_LDT # user-settable LDT; used by WINE
#options MTRR # memory-type range register syscall support
-#options PMC # performance-monitoring counters support
# delay between "rebooting ..." message and hardware reset, in milliseconds
#options CPURESET_DELAY=2000
Index: src/sys/arch/i386/conf/files.i386
diff -u src/sys/arch/i386/conf/files.i386:1.394 src/sys/arch/i386/conf/files.i386:1.395
--- src/sys/arch/i386/conf/files.i386:1.394 Wed May 23 07:45:35 2018
+++ src/sys/arch/i386/conf/files.i386 Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-# $NetBSD: files.i386,v 1.394 2018/05/23 07:45:35 maxv Exp $
+# $NetBSD: files.i386,v 1.395 2018/07/13 09:37:32 maxv Exp $
#
# new style config file for i386 architecture
#
@@ -18,7 +18,6 @@ defparam CPURESET_DELAY
# Obsolete Xbox support
obsolete defflag XBOX
-defflag PMC
defflag KASLR
# User-settable LDT (used by WINE)
Index: src/sys/arch/x86/conf/files.x86
diff -u src/sys/arch/x86/conf/files.x86:1.101 src/sys/arch/x86/conf/files.x86:1.102
--- src/sys/arch/x86/conf/files.x86:1.101 Tue May 22 11:09:57 2018
+++ src/sys/arch/x86/conf/files.x86 Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-# $NetBSD: files.x86,v 1.101 2018/05/22 11:09:57 maxv Exp $
+# $NetBSD: files.x86,v 1.102 2018/07/13 09:37:32 maxv Exp $
# options for MP configuration through the MP spec
defflag opt_mpbios.h MPBIOS MPDEBUG MPBIOS_SCANPCI
@@ -96,7 +96,6 @@ file arch/x86/x86/patch.c machdep
file arch/x86/x86/platform.c machdep
file arch/x86/x86/pmap.c machdep
file arch/x86/x86/x86_tlb.c machdep
-file arch/x86/x86/pmc.c machdep
file arch/x86/x86/procfs_machdep.c procfs
file arch/x86/x86/svs.c machdep & svs
file arch/x86/x86/sys_machdep.c machdep
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.127 src/sys/arch/x86/include/specialreg.h:1.128
--- src/sys/arch/x86/include/specialreg.h:1.127 Wed Jul 4 07:55:57 2018
+++ src/sys/arch/x86/include/specialreg.h Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.127 2018/07/04 07:55:57 maya Exp $ */
+/* $NetBSD: specialreg.h,v 1.128 2018/07/13 09:37:32 maxv Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -930,401 +930,3 @@
#define NCR_SIZE_16M 13
#define NCR_SIZE_32M 14
#define NCR_SIZE_4G 15
-
-/*
- * Performance monitor events.
- *
- * Note that 586-class and 686-class CPUs have different performance
- * monitors available, and they are accessed differently:
- *
- * 686-class: `rdpmc' instruction
- * 586-class: `rdmsr' instruction, CESR MSR
- *
- * The descriptions of these events are too lengthy to include here.
- * See Appendix A of "Intel Architecture Software Developer's
- * Manual, Volume 3: System Programming" for more information.
- */
-
-/*
- * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits
- * is CTR1.
- */
-
-#define PMC5_CESR_EVENT 0x003f
-#define PMC5_CESR_OS 0x0040
-#define PMC5_CESR_USR 0x0080
-#define PMC5_CESR_E 0x0100
-#define PMC5_CESR_P 0x0200
-
-#define PMC5_DATA_READ 0x00
-#define PMC5_DATA_WRITE 0x01
-#define PMC5_DATA_TLB_MISS 0x02
-#define PMC5_DATA_READ_MISS 0x03
-#define PMC5_DATA_WRITE_MISS 0x04
-#define PMC5_WRITE_M_E 0x05
-#define PMC5_DATA_LINES_WBACK 0x06
-#define PMC5_DATA_CACHE_SNOOP 0x07
-#define PMC5_DATA_CACHE_SNOOP_HIT 0x08
-#define PMC5_MEM_ACCESS_BOTH_PIPES 0x09
-#define PMC5_BANK_CONFLICTS 0x0a
-#define PMC5_MISALIGNED_DATA 0x0b
-#define PMC5_INST_READ 0x0c
-#define PMC5_INST_TLB_MISS 0x0d
-#define PMC5_INST_CACHE_MISS 0x0e
-#define PMC5_SEGMENT_REG_LOAD 0x0f
-#define PMC5_BRANCHES 0x12
-#define PMC5_BTB_HITS 0x13
-#define PMC5_BRANCH_TAKEN 0x14
-#define PMC5_PIPELINE_FLUSH 0x15
-#define PMC5_INST_EXECUTED 0x16
-#define PMC5_INST_EXECUTED_V_PIPE 0x17
-#define PMC5_BUS_UTILIZATION 0x18
-#define PMC5_WRITE_BACKUP_STALL 0x19
-#define PMC5_DATA_READ_STALL 0x1a
-#define PMC5_WRITE_E_M_STALL 0x1b
-#define PMC5_LOCKED_BUS 0x1c
-#define PMC5_IO_CYCLE 0x1d
-#define PMC5_NONCACHE_MEM_READ 0x1e
-#define PMC5_AGI_STALL 0x1f
-#define PMC5_FLOPS 0x22
-#define PMC5_BP0_MATCH 0x23
-#define PMC5_BP1_MATCH 0x24
-#define PMC5_BP2_MATCH 0x25
-#define PMC5_BP3_MATCH 0x26
-#define PMC5_HARDWARE_INTR 0x27
-#define PMC5_DATA_RW 0x28
-#define PMC5_DATA_RW_MISS 0x29
-
-/*
- * 686-class Event Selector MSR format.
- */
-
-#define PMC6_EVTSEL_EVENT 0x000000ff
-#define PMC6_EVTSEL_UNIT 0x0000ff00
-#define PMC6_EVTSEL_UNIT_SHIFT 8
-#define PMC6_EVTSEL_USR (1 << 16)
-#define PMC6_EVTSEL_OS (1 << 17)
-#define PMC6_EVTSEL_E (1 << 18)
-#define PMC6_EVTSEL_PC (1 << 19)
-#define PMC6_EVTSEL_INT (1 << 20)
-#define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */
-#define PMC6_EVTSEL_INV (1 << 23)
-#define PMC6_EVTSEL_COUNTER_MASK 0xff000000
-#define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24
-
-/* Data Cache Unit */
-#define PMC6_DATA_MEM_REFS 0x43
-#define PMC6_DCU_LINES_IN 0x45
-#define PMC6_DCU_M_LINES_IN 0x46
-#define PMC6_DCU_M_LINES_OUT 0x47
-#define PMC6_DCU_MISS_OUTSTANDING 0x48
-
-/* Instruction Fetch Unit */
-#define PMC6_IFU_IFETCH 0x80
-#define PMC6_IFU_IFETCH_MISS 0x81
-#define PMC6_ITLB_MISS 0x85
-#define PMC6_IFU_MEM_STALL 0x86
-#define PMC6_ILD_STALL 0x87
-
-/* L2 Cache */
-#define PMC6_L2_IFETCH 0x28
-#define PMC6_L2_LD 0x29
-#define PMC6_L2_ST 0x2a
-#define PMC6_L2_LINES_IN 0x24
-#define PMC6_L2_LINES_OUT 0x26
-#define PMC6_L2_M_LINES_INM 0x25
-#define PMC6_L2_M_LINES_OUTM 0x27
-#define PMC6_L2_RQSTS 0x2e
-#define PMC6_L2_ADS 0x21
-#define PMC6_L2_DBUS_BUSY 0x22
-#define PMC6_L2_DBUS_BUSY_RD 0x23
-
-/* External Bus Logic */
-#define PMC6_BUS_DRDY_CLOCKS 0x62
-#define PMC6_BUS_LOCK_CLOCKS 0x63
-#define PMC6_BUS_REQ_OUTSTANDING 0x60
-#define PMC6_BUS_TRAN_BRD 0x65
-#define PMC6_BUS_TRAN_RFO 0x66
-#define PMC6_BUS_TRANS_WB 0x67
-#define PMC6_BUS_TRAN_IFETCH 0x68
-#define PMC6_BUS_TRAN_INVAL 0x69
-#define PMC6_BUS_TRAN_PWR 0x6a
-#define PMC6_BUS_TRANS_P 0x6b
-#define PMC6_BUS_TRANS_IO 0x6c
-#define PMC6_BUS_TRAN_DEF 0x6d
-#define PMC6_BUS_TRAN_BURST 0x6e
-#define PMC6_BUS_TRAN_ANY 0x70
-#define PMC6_BUS_TRAN_MEM 0x6f
-#define PMC6_BUS_DATA_RCV 0x64
-#define PMC6_BUS_BNR_DRV 0x61
-#define PMC6_BUS_HIT_DRV 0x7a
-#define PMC6_BUS_HITM_DRDV 0x7b
-#define PMC6_BUS_SNOOP_STALL 0x7e
-
-/* Floating Point Unit */
-#define PMC6_FLOPS 0xc1
-#define PMC6_FP_COMP_OPS_EXE 0x10
-#define PMC6_FP_ASSIST 0x11
-#define PMC6_MUL 0x12
-#define PMC6_DIV 0x12
-#define PMC6_CYCLES_DIV_BUSY 0x14
-
-/* Memory Ordering */
-#define PMC6_LD_BLOCKS 0x03
-#define PMC6_SB_DRAINS 0x04
-#define PMC6_MISALIGN_MEM_REF 0x05
-#define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */
-#define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */
-
-/* Instruction Decoding and Retirement */
-#define PMC6_INST_RETIRED 0xc0
-#define PMC6_UOPS_RETIRED 0xc2
-#define PMC6_INST_DECODED 0xd0
-#define PMC6_EMON_KNI_INST_RETIRED 0xd8
-#define PMC6_EMON_KNI_COMP_INST_RET 0xd9
-
-/* Interrupts */
-#define PMC6_HW_INT_RX 0xc8
-#define PMC6_CYCLES_INT_MASKED 0xc6
-#define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
-
-/* Branches */
-#define PMC6_BR_INST_RETIRED 0xc4
-#define PMC6_BR_MISS_PRED_RETIRED 0xc5
-#define PMC6_BR_TAKEN_RETIRED 0xc9
-#define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
-#define PMC6_BR_INST_DECODED 0xe0
-#define PMC6_BTB_MISSES 0xe2
-#define PMC6_BR_BOGUS 0xe4
-#define PMC6_BACLEARS 0xe6
-
-/* Stalls */
-#define PMC6_RESOURCE_STALLS 0xa2
-#define PMC6_PARTIAL_RAT_STALLS 0xd2
-
-/* Segment Register Loads */
-#define PMC6_SEGMENT_REG_LOADS 0x06
-
-/* Clocks */
-#define PMC6_CPU_CLK_UNHALTED 0x79
-
-/* MMX Unit */
-#define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */
-#define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */
-#define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */
-#define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */
-#define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */
-#define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */
-#define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */
-
-/* Segment Register Renaming */
-#define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */
-#define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */
-#define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */
-
-/*
- * AMD K7. [Doc: 22007K.pdf, Feb 2002]
- */
-/* Event Selector MSR format */
-#define K7_EVTSEL_EVENT 0x000000ff
-#define K7_EVTSEL_UNIT 0x0000ff00
-#define K7_EVTSEL_UNIT_SHIFT 8
-#define K7_EVTSEL_USR __BIT(16)
-#define K7_EVTSEL_OS __BIT(17)
-#define K7_EVTSEL_E __BIT(18)
-#define K7_EVTSEL_PC __BIT(19)
-#define K7_EVTSEL_INT __BIT(20)
-#define K7_EVTSEL_EN __BIT(22)
-#define K7_EVTSEL_INV __BIT(23)
-#define K7_EVTSEL_COUNTER_MASK 0xff000000
-#define K7_EVTSEL_COUNTER_MASK_SHIFT 24
-/* Data Cache Unit */
-#define K7_DATA_CACHE_ACCESS 0x40
-#define K7_DATA_CACHE_MISS 0x41
-#define K7_DATA_CACHE_REFILL 0x42
-#define K7_DATA_CACHE_REFILL_SYSTEM 0x43
-#define K7_DATA_CACHE_WBACK 0x44
-#define K7_L1_DTLB_MISS 0x45
-#define K7_L2_DTLB_MISS 0x46
-#define K7_MISALIGNED_DATA_REF 0x47
-/* Instruction Fetch Unit */
-#define K7_IFU_IFETCH 0x80
-#define K7_IFU_IFETCH_MISS 0x81
-#define K7_IFU_REFILL_FROM_L2 0x82
-#define K7_IFU_REFILL_FROM_SYSTEM 0x83
-#define K7_L1_ITLB_MISS 0x84
-#define K7_L2_ITLB_MISS 0x85
-/* Retired */
-#define K7_RETIRED_INST 0xc0
-#define K7_RETIRED_OPS 0xc1
-#define K7_RETIRED_BRANCH 0xc2
-#define K7_RETIRED_BRANCH_MISPREDICTED 0xc3
-#define K7_RETIRED_TAKEN_BRANCH 0xc4
-#define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5
-#define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6
-#define K7_RETIRED_RESYNC_BRANCH 0xc7
-/* Interrupts */
-#define K7_CYCLES_INT_MASKED 0xcd
-#define K7_CYCLES_INT_PENDING_AND_MASKED 0xce
-#define K7_HW_INTR_RECV 0xcf
-
-/*
- * AMD 10h family PMCs. [Doc: 31116.pdf, Jan 2013]
- */
-/* Register MSRs */
-#define MSR_F10H_EVNTSEL0 0xc0010000
-#define MSR_F10H_EVNTSEL1 0xc0010001
-#define MSR_F10H_EVNTSEL2 0xc0010002
-#define MSR_F10H_EVNTSEL3 0xc0010003
-#define MSR_F10H_PERFCTR0 0xc0010004
-#define MSR_F10H_PERFCTR1 0xc0010005
-#define MSR_F10H_PERFCTR2 0xc0010006
-#define MSR_F10H_PERFCTR3 0xc0010007
-/* Event Selector MSR format */
-#define F10H_EVTSEL_EVENT_MASK 0x000F000000FF
-#define F10H_EVTSEL_EVENT_SHIFT_LOW 0
-#define F10H_EVTSEL_EVENT_SHIFT_HIGH 32
-#define F10H_EVTSEL_UNIT_MASK 0x0000FF00
-#define F10H_EVTSEL_UNIT_SHIFT 8
-#define F10H_EVTSEL_USR __BIT(16)
-#define F10H_EVTSEL_OS __BIT(17)
-#define F10H_EVTSEL_EDGE __BIT(18)
-#define F10H_EVTSEL_RSVD1 __BIT(19)
-#define F10H_EVTSEL_INT __BIT(20)
-#define F10H_EVTSEL_RSVD2 __BIT(21)
-#define F10H_EVTSEL_EN __BIT(22)
-#define F10H_EVTSEL_INV __BIT(23)
-#define F10H_EVTSEL_COUNTER_MASK 0xFF000000
-#define F10H_EVTSEL_COUNTER_MASK_SHIFT 24
-/* Floating Point Events */
-#define F10H_FP_DISPATCHED_FPU_OPS 0x00
-#define F10H_FP_CYCLES_EMPTY_FPU_OPS 0x01
-#define F10H_FP_DISPATCHED_FASTFLAG_OPS 0x02
-#define F10H_FP_RETIRED_SSE_OPS 0x03
-#define F10H_FP_RETIRED_MOVE_OPS 0x04
-#define F10H_FP_RETIRED_SERIALIZING_OPS 0x05
-#define F10H_FP_CYCLES_SERIALIZING_OP_SCHEDULER 0x06
-/* Load/Store and TLB Events */
-#define F10H_SEGMENT_REG_LOADS 0x20
-#define F10H_PIPELINE_RESTART_SELFMOD_CODE 0x21
-#define F10H_PIPELINE_RESTART_PROBE_HIT 0x22
-#define F10H_LS_BUFFER_2_FILL 0x23
-#define F10H_LOCKED_OPERATIONS 0x24
-#define F10H_RETIRED_CLFLUSH_INSTRUCTIONS 0x26
-#define F10H_RETIRED_CPUID_INSTRUCTIONS 0x27
-#define F10H_CANCELLED_STORE_LOAD_FORWARD_OPS 0x2A
-#define F10H_SMI_RECEIVED 0x2B
-/* Data Cache Events */
-#define F10H_DATA_CACHE_ACCESS 0x40
-#define F10H_DATA_CACHE_MISS 0x41
-#define F10H_DATA_CACHE_REFILL_FROM_L2 0x42
-#define F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE 0x43
-#define F10H_CACHE_LINES_EVICTED 0x44
-#define F10H_L1_DTLB_MISS 0x45
-#define F10H_L2_DTLB_MISS 0x46
-#define F10H_MISALIGNED_ACCESS 0x47
-#define F10H_MICROARCH_LATE_CANCEL_OF_ACCESS 0x48
-#define F10H_MICROARCH_EARLY_CANCEL_OF_ACCESS 0x49
-#define F10H_SINGLE_BIT_ECC_ERRORS_RECORDED 0x4A
-#define F10H_PREFETCH_INSTRUCTIONS_DISPATCHED 0x4B
-#define F10H_DCACHE_MISSES_LOCKED_INSTRUCTIONS 0x4C
-#define F10H_L1_DTLB_HIT 0x4D
-#define F10H_INEFFECTIVE_SOFTWARE_PREFETCHS 0x52
-#define F10H_GLOBAL_TLB_FLUSHES 0x54
-#define F10H_MEMORY_REQUESTS_BY_TYPE 0x65
-#define F10H_DATA_PREFETCHER 0x67
-#define F10H_MAB_REQUESTS 0x68
-#define F10H_MAB_WAIT_CYCLES 0x69
-#define F10H_NORTHBRIDGE_READ_RESP_BY_COH_STATE 0x6C
-#define F10H_OCTWORDS_WRITTEN_TO_SYSTEM 0x6D
-#define F10H_CPU_CLOCKS_NOT_HALTED 0x76
-#define F10H_REQUESTS_TO_L2_CACHE 0x7D
-#define F10H_L2_CACHE_MISSES 0x7E
-#define F10H_L2_FILL 0x7F
-/* F10H_PAGE_SIZE_MISMATCHES (0x01C0): reserved on some revisions */
-/* Instruction Cache Events */
-#define F10H_INSTRUCTION_CACHE_FETCH 0x80
-#define F10H_INSTRUCTION_CACHE_MISS 0x81
-#define F10H_INSTRUCTION_CACHE_REFILL_FROM_L2 0x82
-#define F10H_INSTRUCTION_CACHE_REFILL_FROM_SYS 0x83
-#define F10H_L1_ITLB_MISS 0x84
-#define F10H_L2_ITLB_MISS 0x85
-#define F10H_PIPELINE_RESTART_INSTR_STREAM_PROBE 0x86
-#define F10H_INSTRUCTION_FETCH_STALL 0x87
-#define F10H_RETURN_STACK_HITS 0x88
-#define F10H_RETURN_STACK_OVERFLOWS 0x89
-#define F10H_INSTRUCTION_CACHE_VICTIMS 0x8B
-#define F10H_INSTRUCTION_CACHE_LINES_INVALIDATED 0x8C
-#define F10H_ITLD_RELOADS 0x99
-#define F10H_ITLD_RELOADS_ABORTED 0x9A
-/* Execution Unit Events */
-#define F10H_RETIRED_INSTRUCTIONS 0xC0
-#define F10H_RETIRED_UOPS 0xC1
-#define F10H_RETIRED_BRANCH 0xC2
-#define F10H_RETIRED_MISPREDICTED_BRANCH 0xC3
-#define F10H_RETIRED_TAKEN_BRANCH 0xC4
-#define F10H_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xC5
-#define F10H_RETIRED_FAR_CONTROL_TRANSFER 0xC6
-#define F10H_RETIRED_BRANCH_RESYNC 0xC7
-#define F10H_RETIRED_NEAR_RETURNS 0xC8
-#define F10H_RETIRED_NEAR_RETURNS_MISPREDICTED 0xC9
-#define F10H_RETIRED_INDIRECT_BRANCH_MISPREDICTED 0xCA
-#define F10H_RETIRED_MMX_FP_INSTRUCTIONS 0xCB
-#define F10H_RETIRED_FASTPATH_DOUBLE_OP_INSTR 0xCC
-#define F10H_INTERRUPTS_MASKED_CYCLES 0xCD
-#define F10H_INTERRUPTS_MASKED_CYCLES_INTERRUPT_PENDING 0xCE
-#define F10H_INTERRUPTS_TAKEN 0xCF
-#define F10H_DECODER_EMPTY 0xD0
-#define F10H_DISPATCH_STALLS 0xD1
-#define F10H_DISPATCH_STALLS_BRANCH_ABORT_RETIRE 0xD2
-#define F10H_DISPATCH_STALLS_SERIALIZATION 0xD3
-#define F10H_DISPATCH_STALLS_SEGMENT_LOAD 0xD4
-#define F10H_DISPATCH_STALLS_REORDER_BUF_FULL 0xD5
-#define F10H_DISPATCH_STALLS_RSV_STATION_FULL 0xD6
-#define F10H_DISPATCH_STALLS_FPU_FULL 0xD7
-#define F10H_DISPATCH_STALLS_LS_FULL 0xD8
-#define F10H_DISPATCH_STALLS_WAITING_ALL_QUITE 0xD9
-#define F10H_DISPATCH_STALLS_FAR_TRANSFER 0xDA
-#define F10H_FPU_EXCEPTIONS 0xDB
-#define F10H_DR0_BREAKPOINT_MATCHES 0xDC
-#define F10H_DR1_BREAKPOINT_MATCHES 0xDD
-#define F10H_DR2_BREAKPOINT_MATCHES 0xDE
-#define F10H_DR3_BREAKPOINT_MATCHES 0xDF
-/* F10H_RETIRED_X87_FP_OPERATIONS (0x01C0): reserved on some revisions */
-/* F10H_IBS_OPS_TAGGED (0x1CF): reserved on some revisions */
-/* F10H_LFENCE_INSTRUCTIONS_RETIRED (0x01D3): reserved on some revisions */
-/* F10H_SFENCE_INSTRUCTIONS_RETIRED (0x01D4): reserved on some revisions */
-/* F10H_MFENCE_INSTRUCTIONS_RETIRED (0x01D5): reserved on some revisions */
-/* Memory Controller Events */
-#define F10H_DRAM_ACCESSES 0xE0
-#define F10H_DRAM_CONTROLLER_PT_OVERFLOWS 0xE1
-#define F10H_MEM_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED 0xE2
-#define F10H_MEM_CONTROLLER_TURNAROUNDS 0xE3
-#define F10H_MEM_CONTROLLER_BYPASS_COUNTER_SATURATION 0xE4
-#define F10H_THERMAL_STATUS 0xE8
-#define F10H_CPU_IO_REQUESTS_TO_MEMORY_IO 0xE9
-#define F10H_CACHE_BLOCK_COMMANDS 0xEA
-#define F10H_SIZED_COMMANDS 0xEB
-#define F10H_PROBE_RESPONSES_AND_UPSTREAM_REQUESTS 0xEC
-#define F10H_GART_EVENTS 0xEE
-#define F10H_MEMORY_CONTROLLER_REQUESTS 0x01F0
-#define F10H_CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE 0x01E0
-#define F10H_IO_TO_DRAM_REQUESTS_TO_TARGET_NODE 0x01E1
-#define F10H_CPU_READ_CMD_LATENCY_TARGET_NODE_03 0x01E2
-#define F10H_CPU_READ_CMD_REQUESTS_TARGET_NODE_03 0x01E3
-#define F10H_CPU_READ_CMD_LATENCY_TARGET_NODE_47 0x01E4
-#define F10H_CPU_READ_CMD_REQUESTS_TARGET_NODE_47 0x01E5
-#define F10H_CPU_CMD_LATENCY_TO_TARGET_NODE_0347 0x01E6
-#define F10H_CPU_REQUESTS_TO_TARGET_NODE_0347 0x01E7
-/* Link Events */
-#define F10H_HYPERTRANSPORT_LINK0_TRANSMIT_BANDWIDTH 0xF6
-#define F10H_HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH 0xF7
-#define F10H_HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH 0xF8
-#define F10H_HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH 0x01F9
-/* L3 Cache Events */
-/* F10H_READ_READ_REQUEST_TO_L3_CACHE (0x04E0): depends on the revision */
-/* F10H_L3_CACHE_MISSES (0x04E1): depends on the revision */
-/* F10H_L3_FILLS_FROM_L2_EVICTIONS (0x04E2): depends on the revision */
-#define F10H_L3_EVICTIONS 0x04E3
-/* F10H_NONCANCELLED_L3_READ_REQUESTS (0x04ED): depends on the revision */
-
Index: src/sys/arch/x86/include/sysarch.h
diff -u src/sys/arch/x86/include/sysarch.h:1.13 src/sys/arch/x86/include/sysarch.h:1.14
--- src/sys/arch/x86/include/sysarch.h:1.13 Thu Jul 12 10:46:47 2018
+++ src/sys/arch/x86/include/sysarch.h Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: sysarch.h,v 1.13 2018/07/12 10:46:47 maxv Exp $ */
+/* $NetBSD: sysarch.h,v 1.14 2018/07/13 09:37:32 maxv Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -38,9 +38,6 @@
#define X86_GET_IOPERM 3
#define X86_SET_IOPERM 4
#define X86_OLD_VM86 5
-#define X86_PMC_INFO 8
-#define X86_PMC_STARTSTOP 9
-#define X86_PMC_READ 10
#define X86_GET_MTRR 11
#define X86_SET_MTRR 12
#define X86_VM86 13
@@ -61,9 +58,6 @@
#define I386_GET_IOPERM X86_GET_IOPERM
#define I386_SET_IOPERM X86_SET_IOPERM
#define I386_OLD_VM86 X86_OLD_VM86
-#define I386_PMC_INFO X86_PMC_INFO
-#define I386_PMC_STARTSTOP X86_PMC_STARTSTOP
-#define I386_PMC_READ X86_PMC_READ
#define I386_GET_MTRR X86_GET_MTRR
#define I386_SET_MTRR X86_SET_MTRR
#define I386_VM86 X86_VM86
@@ -80,9 +74,6 @@
#define X86_64_GET_IOPERM X86_GET_IOPERM
#define X86_64_SET_IOPERM X86_SET_IOPERM
#define X86_64_OLD_VM86 X86_OLD_VM86
-#define X86_64_PMC_INFO X86_PMC_INFO
-#define X86_64_PMC_STARTSTOP X86_PMC_STARTSTOP
-#define X86_64_PMC_READ X86_PMC_READ
#define X86_64_GET_MTRR X86_GET_MTRR
#define X86_64_SET_MTRR X86_SET_MTRR
#define X86_64_VM86 X86_VM86
@@ -130,50 +121,6 @@ struct _X86_SYSARCH_L(set_ioperm_args) {
u_long *iomap;
};
-struct _X86_SYSARCH_L(pmc_info_args) {
- int vers;
- int type;
- uint32_t nctrs;
- uint64_t nsamp;
-};
-
-#define PMC_VERSION 1
-
-#define PMC_TYPE_NONE 0
-#define PMC_TYPE_I586 1
-#define PMC_TYPE_I686 2
-#define PMC_TYPE_K7 3
-#define PMC_TYPE_F10H 4
-
-#define PMC_INFO_HASTSC 0x01
-
-#define PMC_NCOUNTERS 4
-
-struct _X86_SYSARCH_L(pmc_startstop_args) {
- uint32_t counter;
- uint64_t val;
- uint32_t event;
- uint32_t unit;
- uint32_t compare;
- uint32_t flags;
-};
-
-#define PMC_SETUP_KERNEL 0x01
-#define PMC_SETUP_USER 0x02
-#define PMC_SETUP_EDGE 0x04
-#define PMC_SETUP_INV 0x08
-
-typedef struct {
- uint64_t ctrval;
- uint32_t overfl;
-} x86_pmc_cpuval_t;
-
-struct _X86_SYSARCH_L(pmc_read_args) {
- uint32_t counter;
- x86_pmc_cpuval_t *values;
- uint32_t nval;
-};
-
struct mtrr;
#ifdef _KERNEL
@@ -186,23 +133,12 @@ int x86_set_ldt(struct lwp *, void *, re
int x86_set_ldt1(struct lwp *, struct x86_set_ldt_args *, union descriptor *);
int x86_set_sdbase(void *, char, lwp_t *, bool);
int x86_get_sdbase(void *, char);
-
-void pmc_init(void);
-int sys_pmc_info(struct lwp *, struct x86_pmc_info_args *,
- register_t *);
-int sys_pmc_startstop(struct lwp *, struct x86_pmc_startstop_args *,
- register_t *);
-int sys_pmc_read(struct lwp *, struct x86_pmc_read_args *,
- register_t *);
#else
#include <sys/cdefs.h>
__BEGIN_DECLS
int _X86_SYSARCH_L(get_ldt)(int, union descriptor *, int);
int _X86_SYSARCH_L(set_ldt)(int, union descriptor *, int);
int _X86_SYSARCH_L(iopl)(int);
-int _X86_SYSARCH_L(pmc_info)(struct _X86_SYSARCH_L(pmc_info_args *));
-int _X86_SYSARCH_L(pmc_startstop)(struct _X86_SYSARCH_L(pmc_startstop_args *));
-int _X86_SYSARCH_L(pmc_read)(struct _X86_SYSARCH_L(pmc_read_args *));
int _X86_SYSARCH_L(set_mtrr)(struct mtrr *, int *);
int _X86_SYSARCH_L(get_mtrr)(struct mtrr *, int *);
int sysarch(int, void *);
Index: src/sys/arch/x86/x86/sys_machdep.c
diff -u src/sys/arch/x86/x86/sys_machdep.c:1.47 src/sys/arch/x86/x86/sys_machdep.c:1.48
--- src/sys/arch/x86/x86/sys_machdep.c:1.47 Thu Jul 12 10:46:48 2018
+++ src/sys/arch/x86/x86/sys_machdep.c Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: sys_machdep.c,v 1.47 2018/07/12 10:46:48 maxv Exp $ */
+/* $NetBSD: sys_machdep.c,v 1.48 2018/07/13 09:37:32 maxv Exp $ */
/*
* Copyright (c) 1998, 2007, 2009, 2017 The NetBSD Foundation, Inc.
@@ -30,10 +30,9 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sys_machdep.c,v 1.47 2018/07/12 10:46:48 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sys_machdep.c,v 1.48 2018/07/13 09:37:32 maxv Exp $");
#include "opt_mtrr.h"
-#include "opt_pmc.h"
#include "opt_user_ldt.h"
#include "opt_compat_netbsd.h"
#include "opt_xen.h"
@@ -76,7 +75,6 @@ __KERNEL_RCSID(0, "$NetBSD: sys_machdep.
#ifdef XEN
#undef USER_LDT
-#undef PMC
#endif
extern struct vm_map *kernel_map;
@@ -761,20 +759,6 @@ sys_sysarch(struct lwp *l, const struct
error = x86_set_mtrr(l, SCARG(uap, parms), retval);
break;
-#ifdef PMC
- case X86_PMC_INFO:
- error = sys_pmc_info(l, SCARG(uap, parms), retval);
- break;
-
- case X86_PMC_STARTSTOP:
- error = sys_pmc_startstop(l, SCARG(uap, parms), retval);
- break;
-
- case X86_PMC_READ:
- error = sys_pmc_read(l, SCARG(uap, parms), retval);
- break;
-#endif
-
case X86_SET_FSBASE:
error = x86_set_sdbase(SCARG(uap, parms), 'f', curlwp, false);
break;
Index: src/sys/arch/x86/x86/x86_machdep.c
diff -u src/sys/arch/x86/x86/x86_machdep.c:1.118 src/sys/arch/x86/x86/x86_machdep.c:1.119
--- src/sys/arch/x86/x86/x86_machdep.c:1.118 Thu Jul 12 10:46:48 2018
+++ src/sys/arch/x86/x86/x86_machdep.c Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: x86_machdep.c,v 1.118 2018/07/12 10:46:48 maxv Exp $ */
+/* $NetBSD: x86_machdep.c,v 1.119 2018/07/13 09:37:32 maxv Exp $ */
/*-
* Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi,
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: x86_machdep.c,v 1.118 2018/07/12 10:46:48 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: x86_machdep.c,v 1.119 2018/07/13 09:37:32 maxv Exp $");
#include "opt_modular.h"
#include "opt_physmem.h"
@@ -68,7 +68,6 @@ __KERNEL_RCSID(0, "$NetBSD: x86_machdep.
#include <machine/bootinfo.h>
#include <machine/vmparam.h>
-#include <machine/sysarch.h> /* PMC... */
#include <uvm/uvm_extern.h>
@@ -1093,7 +1092,6 @@ x86_startup(void)
{
#if !defined(XEN)
nmi_init();
- pmc_init();
#endif
}
Index: src/sys/arch/xen/conf/files.compat
diff -u src/sys/arch/xen/conf/files.compat:1.30 src/sys/arch/xen/conf/files.compat:1.31
--- src/sys/arch/xen/conf/files.compat:1.30 Mon Jan 8 14:39:33 2018
+++ src/sys/arch/xen/conf/files.compat Fri Jul 13 09:37:32 2018
@@ -1,4 +1,4 @@
-# $NetBSD: files.compat,v 1.30 2018/01/08 14:39:33 maxv Exp $
+# $NetBSD: files.compat,v 1.31 2018/07/13 09:37:32 maxv Exp $
# NetBSD: files.x86,v 1.10 2003/10/08 17:30:00 bouyer Exp
# options for MP configuration through the MP spec
@@ -25,7 +25,6 @@ defflag bioscall.h XXXBIOSCALL
defflag opt_pcibios.h XXXOPT_PCIBIOS
defflag opt_pcifixup.h XXXOPT_PCIFIXUP
-defflag opt_pmc.h XXXPMC
defflag opt_kaslr.h XXXKASLR
defflag opt_svs.h XXXSVS
