Module Name: src Committed By: simonb Date: Sat May 23 10:48:44 UTC 2020
Modified Files:
src/sys/arch/mips/mips: mips_machdep.c
Log Message:
Add SiByte SB-1 rev 0x11 cores and CN70xx CPUs to the CPU table.
To generate a diff of this commit:
cvs rdiff -u -r1.279 -r1.280 src/sys/arch/mips/mips/mips_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
