Module Name: src Committed By: macallan Date: Thu Mar 5 17:42:29 UTC 2015
Modified Files:
src/sys/arch/evbmips/ingenic: intr.c
Log Message:
disable interrupts while processing them, reenable when we're done
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbmips/ingenic/intr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
