Module Name: src Committed By: skrll Date: Tue Jul 26 05:52:55 UTC 2016
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Set the cause register to zero after disabling interrupts now that spl0
doesn't do it.
My cobalt now boots (again again)
To generate a diff of this commit:
cvs rdiff -u -r1.202 -r1.203 src/sys/arch/mips/mips/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
