Module Name: src Committed By: skrll Date: Sun May 7 05:50:39 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Check the TLB entry ASID against base (a0) and limit (a1), and not
limit (a1) and random register value (a2)
While here shave an instruction off
To generate a diff of this commit:
cvs rdiff -u -r1.98 -r1.99 src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
