Module Name: src Committed By: martin Date: Mon Apr 16 14:25:49 UTC 2018
Modified Files: src/share/man/man4 [netbsd-8]: wm.4 src/sys/dev/pci [netbsd-8]: if_wm.c if_wmreg.h if_wmvar.h Log Message: Pull up following revision(s) (requested by msaitoh in ticket #764): sys/dev/pci/if_wm.c: revision 1.567 sys/dev/pci/if_wm.c: revision 1.568 sys/dev/pci/if_wm.c: revision 1.569 sys/dev/pci/if_wmvar.h: revision 1.38 sys/dev/pci/if_wm.c: revision 1.570 sys/dev/pci/if_wm.c: revision 1.571 sys/dev/pci/if_wm.c: revision 1.572 share/man/man4/wm.4: revision 1.40 sys/dev/pci/if_wmreg.h: revision 1.106 sys/dev/pci/if_wmreg.h: revision 1.107 SW PHY Config Enable bit for ICH8 B0 stepping is not bit 1 but bit 0. No binary change: - Sort registers. - Lowercase hexadecimal value. On PCH_SPT (and newer), FLASH access should be done by 32bit. Especially for ICH_FLASH_HSFCTL register, it's located at 0x0006, so it should be accessed via ICH_FLASH_HSFSTS(0x0004) and use shift or mask. Our PCH_SPT part of wm_nvm_valid_bank_detect_ich8lan() was based on FreeBSD r287467. After that, they reverted it and committed the different code in r287762. r287762's bank detect code didn't work for us because our wm dirver had a problem in flash access. The problem was fixed in if_wm.c rev. 1.567, so we can use the new way now. If the extended configration size in the EXTCNFSIZE register is 0, don't continue. Add PCH_CNP support (I219 with Intel 300 series chipset). It's required more test, so it's disabled by default. Enable I219. I354 uses an external PHY, so don't use wm_set_eee_i350(). To generate a diff of this commit: cvs rdiff -u -r1.36.4.1 -r1.36.4.2 src/share/man/man4/wm.4 cvs rdiff -u -r1.508.4.16 -r1.508.4.17 src/sys/dev/pci/if_wm.c cvs rdiff -u -r1.98.6.3 -r1.98.6.4 src/sys/dev/pci/if_wmreg.h cvs rdiff -u -r1.33.6.1 -r1.33.6.2 src/sys/dev/pci/if_wmvar.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.