Module Name: src Committed By: cherry Date: Mon Feb 11 17:28:52 UTC 2019
Modified Files:
src/sys/arch/i386/i386: i386_trap.S
Log Message:
Remove redundant conditional IDT_VEC() entries.
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/i386/i386/i386_trap.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
