Module Name: src Committed By: jakllsch Date: Wed Dec 18 18:40:19 UTC 2019
Modified Files: src/sys/arch/arm/rockchip: rk3399_cru.c Log Message: rk3399_cru: Reparent dclk_vop[01] to gpll via dclk_vop[01]_frac. The previous source of dclk_vop[01] was vpll via dclk_vop[01]_div. vpll is apparently used directly as a pixel clock source for the HDMI PHY, and we don't want the other VOP's dclk changing out from under it because we can't handle finding a replacement clock source with the right rate yet. gpll happens to run at 594MHz, which works well as a basis for pixel clocks. Linux suggests that the source clock of the fractional divider needs to be more than twenty times greater than the resulting clock (or some intermediate clock?) for output stability. This may not be the case with 594MHz and the common pixel clocks I see used by displays in my area of the wild, but it works for now. To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/rockchip/rk3399_cru.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.