CVSROOT: /cvs Module name: src Changes by: [email protected] 2019/02/21 15:44:44
Modified files:
sys/dev/usb : xhci.c
Log message:
Transfers that span multiple TRBs which wrap around the ring and
thus have the Link TRB inbetween must have the Chain Bit set in the
Link TRB. Otherwise xHCI controllers might think that the transfer
ends at that point.
Fixes an issue that was most prominently seen as Invalid CSW error
when using umass0 on octeon and i.MX8M.
Tested by visa@
ok mpi@
